From patchwork Fri Oct 25 03:55:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13850017 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACB8618C009; Fri, 25 Oct 2024 03:56:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828586; cv=none; b=DaBDQbi4hN5EcKOsyyUbpVtHk5xgWJwz+IVA0POesJu13rD1/couuxQkU8Uh1Lj+ihdbbLwv59U5piL6ylW1+HhzXUPqNVBQKZNRbgL/rUgmiBk2vtDYIxoLi2ffRW8LOwtbCC9lHrcWhF3WiV2GiQUOp06pL1J43pthncNCVlg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828586; c=relaxed/simple; bh=pjkDNtLRl1TxZ8GlevZCOWRgBrcRw/LC4IONqX6y+0U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NWK2TINl0Hiz9fd5hMD40a/7ek7ouBS9IvPXzJKTBCI4y/R23uJ+dqof9Hv2DeE8OdS881LABF3at5Fmbb8hGEL50HSwPDzPIwzUsahwcV2wjdC+Y4kVe44OBrEdVtMZf+Hvo2kMS7CmB6fGaOCCZuAVTtJqKbj3sDsbRUDNxBs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=aW6XBAgj; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="aW6XBAgj" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49OJn7JL018657; Fri, 25 Oct 2024 03:56:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= QysM8CLXknciTUXr+RGhpBn14VHz11If4slYyVFUnkg=; b=aW6XBAgjeo3lzoAw /5lIR5dgX/YMzN4g0CFjUvlWzQV8vD4/cpXUpEZTlYgWSI5XlxQJ59DAnJaehyzf V6htq1rKu+cJkD2HVrk/HRwB1NmYpn/reJ/i7xItG3+bynHr0x0OI1WGLZwn9QQH EstF2EKYg0a1DABDw+KX9NTty+A11+WLEJWauP++pyis0Gou3ibTFL51v7cPbT2q YWqjLvlvyPAPy9p5wqw86ZAPQx9P/Iz3V+sFIzi052cBqXfyIwm6qh3G1A5557ta tv5ijq9tj/H3l2yClY/lGRZVutmqzeFmA+sI3Hh6YpwXuj9cvkptsElsPjb5vHgj UZeLjg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42em66fp8f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:56:06 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49P3u51x015540 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:56:05 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 20:55:57 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v8 3/7] clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock Date: Fri, 25 Oct 2024 09:25:16 +0530 Message-ID: <20241025035520.1841792-4-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> References: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Z6_UI6uDbeIle-h0t14nPPUY1UawDfkV X-Proofpoint-GUID: Z6_UI6uDbeIle-h0t14nPPUY1UawDfkV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 clxscore=1015 mlxscore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250026 From: Devi Priya Add support for gpll0_out_aux clock which acts as the parent for certain networking subsystem (nss) clocks. Reviewed-by: Dmitry Baryshkov Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - No change drivers/clk/qcom/gcc-ipq9574.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 0405a2473842..08921bff46da 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -108,6 +108,20 @@ static struct clk_alpha_pll_postdiv gpll0 = { }, }; +static struct clk_alpha_pll_postdiv gpll0_out_aux = { + .offset = 0x20000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpll0_out_aux", + .parent_hws = (const struct clk_hw *[]) { + &gpll0_main.clkr.hw + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + static struct clk_alpha_pll gpll4_main = { .offset = 0x22000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], @@ -4222,6 +4236,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, + [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = {