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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e1c7cf4sm532188e87.184.2024.10.26.08.47.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Oct 2024 08:47:13 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 26 Oct 2024 18:47:03 +0300 Subject: [PATCH v4 05/11] dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241026-sar2130p-clocks-v4-5-37100d40fadc@linaro.org> References: <20241026-sar2130p-clocks-v4-0-37100d40fadc@linaro.org> In-Reply-To: <20241026-sar2130p-clocks-v4-0-37100d40fadc@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3379; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=U8SwElc6O/aMG3Pi0A0hWuxY5S0AlYAxeI/Vjj5b5Qw=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnHQ73wf+2XaraKbcpddGfJTvt+qMC231yarFzI MOKrPI+1oCJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZx0O9wAKCRAU23LtvoBl uKnEEAC2FgG1oWLGXVi5s+pt9FVUYcleKOsm7F+xtrqocWbj4FnYfR08EYdKb40qiXEE2g+Hw0u SPJIrbXeiojLv4/oXe9DA8ZWk2IQF4wkqLgx8cU2etwNNBS077/Pie2sLMhYjdpU5TEX7CLj9d0 ByTX2VwR/h/rVXOivo6k3JrksbQAhVhkwG8s+OLG9D3A3VtIt2wnFlso2D6yY8rog/5IwrlHjy/ rOnos48D+1wes3UtyEn84ZBmI+yi2XgE92V+RiX84J78J5qXqRddQM47qKJTywhYBfnvBdMaMX+ mT5VEb94oepTmCA97Sp6lfS8MaVr42YzqLJH4IktPLyiuUySWd5vXYyUdBRFvytnhtmmpYu1sGu U++A2MSAkHLr5ACC8Jhlu0JOxVHjG//tnq+cOXMw1dtq8nUuBxX5MV9lqx/njKZZB/KWQJ97y/U 4L/n62q5ds9Ucxg6INZ1zmnZg9DpeJD3A5P+Kry9PdGjmi9SlYZbYwHBSeScV/DgD4+p6cfiJ9T dG8akoV678RgJOWvV1xi2JS4JMf6R0Gri+I7SlLC3A3Djjqmx4LBh9hettJOYxUVCFgbjPnLofu 5oNIfXARMKGDO7xGymPKRwgrtUu0DiC0EfXgAx0saWYfBZNvQOakmoE5rKaWmTWKcUmqj4fzAh7 0h5cxoJgL4hdgQQ== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A From: Konrad Dybcio Expand qcom,sm8450-gpucc bindings to include SAR2130P. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 ++ include/dt-bindings/clock/qcom,sar2130p-gpucc.h | 33 ++++++++++++++++++++++ include/dt-bindings/reset/qcom,sar2130p-gpucc.h | 14 +++++++++ 3 files changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index b9d29e4f65ded538c0ac8caae5acb541c9f01f41..5c65f5ecf0f387f30ae70a8f2b25d292f6092133 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -14,6 +14,7 @@ description: | domains on Qualcomm SoCs. See also:: + include/dt-bindings/clock/qcom,sar2130p-gpucc.h include/dt-bindings/clock/qcom,sm4450-gpucc.h include/dt-bindings/clock/qcom,sm8450-gpucc.h include/dt-bindings/clock/qcom,sm8550-gpucc.h @@ -24,6 +25,7 @@ description: | properties: compatible: enum: + - qcom,sar2130p-gpucc - qcom,sm4450-gpucc - qcom,sm8450-gpucc - qcom,sm8475-gpucc diff --git a/include/dt-bindings/clock/qcom,sar2130p-gpucc.h b/include/dt-bindings/clock/qcom,sar2130p-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..a2204369110a585394d175193dce8bf9f63439d2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sar2130p-gpucc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved + * Copyright (c) 2024, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_FF_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CXO_AON_CLK 4 +#define GPU_CC_CXO_CLK 5 +#define GPU_CC_FF_CLK_SRC 6 +#define GPU_CC_GMU_CLK_SRC 7 +#define GPU_CC_GX_GMU_CLK 8 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 9 +#define GPU_CC_HUB_AON_CLK 10 +#define GPU_CC_HUB_CLK_SRC 11 +#define GPU_CC_HUB_CX_INT_CLK 12 +#define GPU_CC_MEMNOC_GFX_CLK 13 +#define GPU_CC_PLL0 14 +#define GPU_CC_PLL1 15 +#define GPU_CC_SLEEP_CLK 16 + +/* GDSCs */ +#define GPU_GX_GDSC 0 +#define GPU_CX_GDSC 1 + +#endif diff --git a/include/dt-bindings/reset/qcom,sar2130p-gpucc.h b/include/dt-bindings/reset/qcom,sar2130p-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..99ba5f092e2a43fb7b7b2a9f78d9ac4ae0bfea18 --- /dev/null +++ b/include/dt-bindings/reset/qcom,sar2130p-gpucc.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SAR2130P_H +#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SAR2130P_H + +#define GPUCC_GPU_CC_GX_BCR 0 +#define GPUCC_GPU_CC_ACD_BCR 1 +#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 2 + +#endif