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Thu, 31 Oct 2024 07:15:13 GMT Received: from jingyw-gv.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 31 Oct 2024 00:15:09 -0700 From: Jingyi Wang Date: Thu, 31 Oct 2024 15:14:38 +0800 Subject: [PATCH v3 3/3] arm64: dts: qcom: qcs8300: Add LLCC support for QCS8300 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241031-qcs8300_llcc-v3-3-bb56952cb83b@quicinc.com> References: <20241031-qcs8300_llcc-v3-0-bb56952cb83b@quicinc.com> In-Reply-To: <20241031-qcs8300_llcc-v3-0-bb56952cb83b@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , Jingyi Wang , <20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com>, <20241026-sar2130p-llcc-v3-0-2a58fa1b4d12@linaro.org>, Konrad Dybcio X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; 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Reviewed-by: Konrad Dybcio Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 2c35f96c3f28..811c926c94f4 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -882,6 +882,21 @@ gem_noc: interconnect@9100000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + llcc: system-cache-controller@9200000 { + compatible = "qcom,qcs8300-llcc"; + reg = <0x0 0x09200000 0x0 0x80000>, + <0x0 0x09300000 0x0 0x80000>, + <0x0 0x09400000 0x0 0x80000>, + <0x0 0x09500000 0x0 0x80000>, + <0x0 0x09a00000 0x0 0x80000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc_broadcast_base"; + interrupts = ; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,qcs8300-pdc", "qcom,pdc"; reg = <0x0 0xb220000 0x0 0x30000>,