| Message ID | 20241101030902.579789-4-quic_qianyu@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Add support for PCIe3 on x1e80100 | expand |
On Thu, Oct 31, 2024 at 08:09:00PM -0700, Qiang Yu wrote: > The SC8280XP PCIe devicetree nodes do not specify an 'iommu-map' so the > config_sid() callback is effectively a no-op. Hence introduce a new ops Would have been good to say something about why there are no 'iommu-map' properties on sc8280xp (e.g. since it uses an SMMUv3) as Bjorn suggested. > struct, namely ops_1_21_0 which is same as ops_1_9_0 except that it > doesn't have config_sid() callback to clean it up. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> I see that this patch has been picked up now. The above is already much better and I guess this is good enough for now: Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Hello, [...] > Would have been good to say something about why there are no 'iommu-map' > properties on sc8280xp (e.g. since it uses an SMMUv3) as Bjorn > suggested. Happy to update the commit log directly if there is a consensus about how the final wording should look like. > > struct, namely ops_1_21_0 which is same as ops_1_9_0 except that it > > doesn't have config_sid() callback to clean it up. > > > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > I see that this patch has been picked up now. The above is already much > better and I guess this is good enough for now: > > Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Added. Thank you! Krzysztof
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index ef44a82be058..52e3d71028d8 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1364,6 +1364,16 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .config_sid = qcom_pcie_config_sid_1_9_0, }; +/* Qcom IP rev.: 1.21.0 Synopsys IP rev.: 5.60a */ +static const struct qcom_pcie_ops ops_1_21_0 = { + .get_resources = qcom_pcie_get_resources_2_7_0, + .init = qcom_pcie_init_2_7_0, + .post_init = qcom_pcie_post_init_2_7_0, + .host_post_init = qcom_pcie_host_post_init_2_7_0, + .deinit = qcom_pcie_deinit_2_7_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, +}; + /* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */ static const struct qcom_pcie_ops ops_2_9_0 = { .get_resources = qcom_pcie_get_resources_2_9_0, @@ -1411,7 +1421,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = { }; static const struct qcom_pcie_cfg cfg_sc8280xp = { - .ops = &ops_1_9_0, + .ops = &ops_1_21_0, .no_l0s = true, };