diff mbox series

[v2,2/2] arm64: dts: qcom: sa8775p: Add LMH interrupts for cpufreq_hw node

Message ID 20241112-sa8775p-cpufreq-l3-ddr-scaling-v2-2-53d256b3f2a7@quicinc.com (mailing list archive)
State New
Headers show
Series Add support to scale DDR and L3 on SA8775P | expand

Commit Message

Jagadeesh Kona Nov. 12, 2024, 12:44 p.m. UTC 
Add LMH interrupts for cpufreq_hw node to indicate if there is any
thermal throttle.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 1d2b45bde03fa28b47639ce4f4d7c38e352d84de..9a03a87bf2026516b6deb3bf3e87c7af95bebea1 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -4510,6 +4510,10 @@  cpufreq_hw: cpufreq@18591000 {
 			      <0x0 0x18593000 0x0 0x1000>;
 			reg-names = "freq-domain0", "freq-domain1";
 
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
+
 			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
 			clock-names = "xo", "alternate";