| Message ID | 20241121113006.28520-3-quic_rlaggysh@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add EPSS L3 provider support on SA8775P SoC | expand |
On 21/11/2024 12:30, Raviteja Laggyshetty wrote: > Add Epoch Subsystem (EPSS) L3 interconnect provider node on SA8775P > SoCs. > > Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 9f315a51a7c1..dd7207eb3616 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -10,6 +10,7 @@ > #include <dt-bindings/clock/qcom,sa8775p-gcc.h> > #include <dt-bindings/clock/qcom,sa8775p-gpucc.h> > #include <dt-bindings/dma/qcom-gpi.h> > +#include <dt-bindings/interconnect/qcom,osm-l3.h> > #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> > #include <dt-bindings/mailbox/qcom-ipcc.h> > #include <dt-bindings/firmware/qcom,scm.h> > @@ -4282,6 +4283,15 @@ rpmhpd_opp_turbo_l1: opp-9 { > }; > }; > > + epss_l3_cl0: interconnect@18590000 { Drop unused label. BTW, DTS is never before the driver. It suggests dependency. If you have dependency, it's a NAK. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 9f315a51a7c1..dd7207eb3616 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/clock/qcom,sa8775p-gcc.h> #include <dt-bindings/clock/qcom,sa8775p-gpucc.h> #include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/firmware/qcom,scm.h> @@ -4282,6 +4283,15 @@ rpmhpd_opp_turbo_l1: opp-9 { }; }; + epss_l3_cl0: interconnect@18590000 { + compatible = "qcom,sa8775p-epss-l3", + "qcom,epss-l3-perf"; + reg = <0x0 0x18590000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,sa8775p-cpufreq-epss", "qcom,cpufreq-epss"; @@ -4295,6 +4305,15 @@ cpufreq_hw: cpufreq@18591000 { #freq-domain-cells = <1>; }; + epss_l3_cl1: interconnect@18592000 { + compatible = "qcom,sa8775p-epss-l3", + "qcom,epss-l3-perf"; + reg = <0x0 0x18592000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + remoteproc_gpdsp0: remoteproc@20c00000 { compatible = "qcom,sa8775p-gpdsp0-pas"; reg = <0x0 0x20c00000 0x0 0x10000>;
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SA8775P SoCs. Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)