@@ -588,7 +588,7 @@ static const struct msm_mdss_data sa8775p_data = {
.ubwc_swizzle = 4,
.ubwc_bank_spread = true,
.highest_bank_bit = 0,
- .macrotile_mode = 1,
+ .macrotile_mode = true,
.reg_bus_bw = 74000,
};
@@ -607,7 +607,7 @@ static const struct msm_mdss_data sc7280_data = {
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
.highest_bank_bit = 1,
- .macrotile_mode = 1,
+ .macrotile_mode = true,
.reg_bus_bw = 74000,
};
@@ -615,7 +615,7 @@ static const struct msm_mdss_data sc8180x_data = {
.ubwc_enc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
.highest_bank_bit = 3,
- .macrotile_mode = 1,
+ .macrotile_mode = true,
.reg_bus_bw = 76800,
};
@@ -625,7 +625,7 @@ static const struct msm_mdss_data sc8280xp_data = {
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
.highest_bank_bit = 3,
- .macrotile_mode = 1,
+ .macrotile_mode = true,
.reg_bus_bw = 76800,
};
@@ -689,7 +689,7 @@ static const struct msm_mdss_data sm8250_data = {
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
.highest_bank_bit = 3,
- .macrotile_mode = 1,
+ .macrotile_mode = true,
.reg_bus_bw = 76800,
};
@@ -700,7 +700,7 @@ static const struct msm_mdss_data sm8350_data = {
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
.highest_bank_bit = 3,
- .macrotile_mode = 1,
+ .macrotile_mode = true,
.reg_bus_bw = 74000,
};
@@ -711,7 +711,7 @@ static const struct msm_mdss_data sm8550_data = {
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
.highest_bank_bit = 3,
- .macrotile_mode = 1,
+ .macrotile_mode = true,
.reg_bus_bw = 57000,
};
@@ -722,7 +722,7 @@ static const struct msm_mdss_data x1e80100_data = {
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
.highest_bank_bit = 3,
- .macrotile_mode = 1,
+ .macrotile_mode = true,
/* TODO: Add reg_bus_bw with real value */
};
@@ -13,7 +13,7 @@ struct msm_mdss_data {
u32 ubwc_swizzle;
u32 highest_bank_bit;
bool ubwc_bank_spread;
- u32 macrotile_mode;
+ bool macrotile_mode;
u32 reg_bus_bw;
};