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Thu, 28 Nov 2024 11:56:33 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 28 Nov 2024 03:56:27 -0800 From: Tingguo Cheng Date: Thu, 28 Nov 2024 19:55:26 +0800 Subject: [PATCH v5 2/3] arm64: dts: qcom: qcs615-ride: Enable PMIC peripherals Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241128-adds-spmi-pmic-peripherals-for-qcs615-v5-2-ae673596b71c@quicinc.com> References: <20241128-adds-spmi-pmic-peripherals-for-qcs615-v5-0-ae673596b71c@quicinc.com> In-Reply-To: <20241128-adds-spmi-pmic-peripherals-for-qcs615-v5-0-ae673596b71c@quicinc.com> To: , , , , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Tingguo Cheng X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=ed25519-sha256; t=1732794978; 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Signed-off-by: Tingguo Cheng --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index ee6cab3924a6d71f29934a8debba3a832882abdd..4e2f39c78546b4a2a95914fd4aa55d92b9670cb5 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -6,6 +6,7 @@ #include #include "qcs615.dtsi" +#include "pm8150.dtsi" / { model = "Qualcomm Technologies, Inc. QCS615 Ride"; compatible = "qcom,qcs615-ride", "qcom,qcs615"; @@ -202,6 +203,16 @@ &gcc { <&sleep_clk>; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; };