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a=openpgp-sha256; l=844; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Hw/hyP5k8e4mrPZ2Xq4xWEV8pyteJA9D67U7usPU5R4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm3z0aH5MHMf2dYty9WKiYyDzF4pWI5O9Wf18 dfEKdqrOkKJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt8wAKCRCLPIo+Aiko 1foACACUUWqTouCfHxP5WGemewoFWQwGeF6/iAMEXGy2HPgcqw4JjAlfC6KXkhWeSFjiWxnLDSs GsJocutQLttSycnZJHGe4DlqKirCuVxlgy6ig0ztCT1tVBsaxmL6+dIn0VWPwewqyieLtenfjlE NJeDMW+CG7rfltYPc0j3aYNcWoErr257Cu1XpfFsChTsYLqsMZfoNnnmCCGYM5sSwoqx3VuR7Kz /jwbYYL+mvb2no+NLPweKxgJ+p3+oUxPKTePo0LZ5xGSuHxAV2A3pBGl/XHpnictm/p4JIB4dN+ 89JdoeJ3ltk6DFF4kzgLX7q1kBpsXDJZ7RJX4km9yShTXChO X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Qualcomm RB2 board uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 8d58a8c0d930 ("arm64: dts: qcom: Add base qrb4210-rb2 board dts") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index a9540e92d3e6fc314fa91d4f055325680233f6c4..d8d4cff7d5abed405d1b4cdf9ab8264aab076830 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -545,7 +545,7 @@ can@0 { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &tlmm {