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Wed, 4 Dec 2024 19:37:41 GMT Received: from hu-molvera-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Dec 2024 11:37:40 -0800 From: Melody Olvera Date: Wed, 4 Dec 2024 11:37:19 -0800 Subject: [PATCH v3 7/8] dt-bindings: clock: qcom: Document the SM8750 TCSR Clock Controller Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241204-sm8750_master_clks-v3-7-1a8f31a53a86@quicinc.com> References: <20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com> In-Reply-To: <20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das CC: , , , , Melody Olvera , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733341058; l=2005; i=quic_molvera@quicinc.com; s=20241204; h=from:subject:message-id; bh=ySYPgeVBwlX6fAJgBZVf8FK/j8AMPcK1DVz9NNfgaSs=; b=zmSQIF7H9jW7r4O5gFvjtVG/PPhD1q2X7mmG2/FEK5Hwt1Oi3Y+pUIA4pSgApwKKlFuR+qiLS ymZC0mJ5i9vDFIOCfK8xaAe0PmsNqWCBMZF6gDPmhWFr0eKGf7BAbWO X-Developer-Key: i=quic_molvera@quicinc.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: aaXGufzUCgnbHnsa9Aauj5PFSEWIcuAP X-Proofpoint-GUID: aaXGufzUCgnbHnsa9Aauj5PFSEWIcuAP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 bulkscore=0 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 mlxscore=0 spamscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412040150 From: Taniya Das Add bindings documentation for the SM8750 Clock Controller. Acked-by: Krzysztof Kozlowski Signed-off-by: Melody Olvera Signed-off-by: Taniya Das --- .../devicetree/bindings/clock/qcom,sm8550-tcsr.yaml | 2 ++ include/dt-bindings/clock/qcom,sm8750-tcsr.h | 15 +++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 3b546deb514af2ffe35d80337335509e8f6a559d..f3afbb25e8682de83fb16acaa35448545f77ce77 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -16,6 +16,7 @@ description: | See also: - include/dt-bindings/clock/qcom,sm8550-tcsr.h - include/dt-bindings/clock/qcom,sm8650-tcsr.h + - include/dt-bindings/clock/qcom,sm8750-tcsr.h properties: compatible: @@ -24,6 +25,7 @@ properties: - qcom,sar2130p-tcsr - qcom,sm8550-tcsr - qcom,sm8650-tcsr + - qcom,sm8750-tcsr - qcom,x1e80100-tcsr - const: syscon diff --git a/include/dt-bindings/clock/qcom,sm8750-tcsr.h b/include/dt-bindings/clock/qcom,sm8750-tcsr.h new file mode 100644 index 0000000000000000000000000000000000000000..1c502ac7c7f40807f930583301e9b7b73ebea477 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-tcsr.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H + +/* TCSR_CC clocks */ +#define TCSR_PCIE_0_CLKREF_EN 0 +#define TCSR_UFS_CLKREF_EN 1 +#define TCSR_USB2_CLKREF_EN 2 +#define TCSR_USB3_CLKREF_EN 3 + +#endif