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Wed, 4 Dec 2024 19:37:41 GMT Received: from hu-molvera-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Dec 2024 11:37:40 -0800 From: Melody Olvera Date: Wed, 4 Dec 2024 11:37:20 -0800 Subject: [PATCH v3 8/8] clk: qcom: Add TCSR clock driver for SM8750 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241204-sm8750_master_clks-v3-8-1a8f31a53a86@quicinc.com> References: <20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com> In-Reply-To: <20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das CC: , , , , Melody Olvera , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733341058; l=5873; i=quic_molvera@quicinc.com; s=20241204; h=from:subject:message-id; bh=1Mp+WlHTxiM3PsgMyVlzQAdVtkDxYE8FHogcGVcpFv8=; b=S7dIL9SDZsHvAJsGGxtZhALocnPxf/JQz9CVC5Jrf67j1xhS3N/m0Py+YLZq1gj+vy8hxBJab IbKKKENbxIaALKxLXqTsm4Slw/2zO7d/cd1SuTt2kOxfABkDV/4HYWB X-Developer-Key: i=quic_molvera@quicinc.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: oE5aW6lD0DKBAL2pc-HN4DaorEGja3Fb X-Proofpoint-ORIG-GUID: oE5aW6lD0DKBAL2pc-HN4DaorEGja3Fb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=845 mlxscore=0 suspectscore=0 spamscore=0 malwarescore=0 adultscore=0 priorityscore=1501 clxscore=1015 phishscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412040150 From: Taniya Das The TCSR clock controller found on SM8750 provides refclks for PCIE, USB and UFS. Add clock driver for it. Signed-off-by: Melody Olvera Reviewed-by: Dmitry Baryshkov Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 8 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/tcsrcc-sm8750.c | 141 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 150 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 26bfb607235bf3689744532e4f7c087606846b12..2ec9be21ff678e3343cccafa85801aa68805f440 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1255,6 +1255,14 @@ config SM_TCSRCC_8650 Support for the TCSR clock controller on SM8650 devices. Say Y if you want to use peripheral devices such as SD/UFS. +config SM_TCSRCC_8750 + tristate "SM8750 TCSR Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the TCSR clock controller on SM8750 devices. + Say Y if you want to use peripheral devices such as UFS/USB/PCIe. + config SA_VIDEOCC_8775P tristate "SA8775P Video Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 1875018d1100f57a475d9cf6b2a267a7a87680be..28e45316627afed09b76ffe4a8ad727ced455347 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -157,6 +157,7 @@ obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o +obj-$(CONFIG_SM_TCSRCC_8750) += tcsrcc-sm8750.o obj-$(CONFIG_SM_VIDEOCC_7150) += videocc-sm7150.o obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o diff --git a/drivers/clk/qcom/tcsrcc-sm8750.c b/drivers/clk/qcom/tcsrcc-sm8750.c new file mode 100644 index 0000000000000000000000000000000000000000..242e320986ef6a54d6bb1a8996d822eda461789b --- /dev/null +++ b/drivers/clk/qcom/tcsrcc-sm8750.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-branch.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" + +enum { + DT_BI_TCXO_PAD, +}; + +static struct clk_branch tcsr_pcie_0_clkref_en = { + .halt_reg = 0x0, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_pcie_0_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_clkref_en = { + .halt_reg = 0x1000, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_ufs_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_clkref_en = { + .halt_reg = 0x2000, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_usb2_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_clkref_en = { + .halt_reg = 0x3000, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x3000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_usb3_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *tcsr_cc_sm8750_clocks[] = { + [TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr, + [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr, + [TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr, + [TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr, +}; + +static const struct regmap_config tcsr_cc_sm8750_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x3000, + .fast_io = true, +}; + +static const struct qcom_cc_desc tcsr_cc_sm8750_desc = { + .config = &tcsr_cc_sm8750_regmap_config, + .clks = tcsr_cc_sm8750_clocks, + .num_clks = ARRAY_SIZE(tcsr_cc_sm8750_clocks), +}; + +static const struct of_device_id tcsr_cc_sm8750_match_table[] = { + { .compatible = "qcom,sm8750-tcsr" }, + { } +}; +MODULE_DEVICE_TABLE(of, tcsr_cc_sm8750_match_table); + +static int tcsr_cc_sm8750_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &tcsr_cc_sm8750_desc); +} + +static struct platform_driver tcsr_cc_sm8750_driver = { + .probe = tcsr_cc_sm8750_probe, + .driver = { + .name = "tcsr_cc-sm8750", + .of_match_table = tcsr_cc_sm8750_match_table, + }, +}; + +static int __init tcsr_cc_sm8750_init(void) +{ + return platform_driver_register(&tcsr_cc_sm8750_driver); +} +subsys_initcall(tcsr_cc_sm8750_init); + +static void __exit tcsr_cc_sm8750_exit(void) +{ + platform_driver_unregister(&tcsr_cc_sm8750_driver); +} +module_exit(tcsr_cc_sm8750_exit); + +MODULE_DESCRIPTION("QTI TCSR_CC SM8750 Driver"); +MODULE_LICENSE("GPL");