| Message ID | 20241204113329.3195627-7-quic_varada@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add PCIe support for Qualcomm IPQ5332 | expand |
On 4.12.2024 12:33 PM, Varadarajan Narayanan wrote: > From: Praveenkumar I <quic_ipkumar@quicinc.com> > > Enable the PCIe controller and PHY nodes for RDP 441. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 74 +++++++++++++++++++++ > 1 file changed, 74 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts > index 846413817e9a..83eca8435cff 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts > +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts > @@ -62,4 +62,78 @@ data-pins { > bias-pull-up; > }; > }; > + > + pcie0_default: pcie0-default-state { > + clkreq-n-pins { > + pins = "gpio37"; > + function = "pcie0_clk"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + > + perst-n-pins { > + pins = "gpio38"; > + function = "gpio"; > + drive-strength = <8>; > + bias-pull-up; > + output-low; > + }; > + > + wake-n-pins { > + pins = "gpio39"; > + function = "pcie0_wake"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > + > + pcie1_default: pcie1-default-state { > + clkreq-n-pins { > + pins = "gpio46"; > + function = "pcie1_clk"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + > + perst-n-pins { > + pins = "gpio47"; > + function = "gpio"; > + drive-strength = <8>; > + bias-pull-up; > + output-low; > + }; > + > + wake-n-pins { > + pins = "gpio48"; > + function = "pcie1_wake"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > +}; > + > +&pcie0_phy { > + status = "okay"; > +}; 'p' < 't', please put this before &tlmm Also, would this be something to put into rdp-common? Do we still use all of these variants? $ ls arch/arm64/boot/dts/qcom/ipq5332-rdp*.dts arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts Konrad
On 4.12.2024 12:33 PM, Varadarajan Narayanan wrote: Subject: arm64: dts: qcom: ipq5332-rdp441: xyz abc Konrad
On Thu, Dec 05, 2024 at 05:58:19PM +0100, Konrad Dybcio wrote: > On 4.12.2024 12:33 PM, Varadarajan Narayanan wrote: > > From: Praveenkumar I <quic_ipkumar@quicinc.com> > > > > Enable the PCIe controller and PHY nodes for RDP 441. > > > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > > --- > > arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 74 +++++++++++++++++++++ > > 1 file changed, 74 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts > > index 846413817e9a..83eca8435cff 100644 > > --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts > > +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts > > @@ -62,4 +62,78 @@ data-pins { > > bias-pull-up; > > }; > > }; > > + > > + pcie0_default: pcie0-default-state { > > + clkreq-n-pins { > > + pins = "gpio37"; > > + function = "pcie0_clk"; > > + drive-strength = <8>; > > + bias-pull-up; > > + }; > > + > > + perst-n-pins { > > + pins = "gpio38"; > > + function = "gpio"; > > + drive-strength = <8>; > > + bias-pull-up; > > + output-low; > > + }; > > + > > + wake-n-pins { > > + pins = "gpio39"; > > + function = "pcie0_wake"; > > + drive-strength = <8>; > > + bias-pull-up; > > + }; > > + }; > > + > > + pcie1_default: pcie1-default-state { > > + clkreq-n-pins { > > + pins = "gpio46"; > > + function = "pcie1_clk"; > > + drive-strength = <8>; > > + bias-pull-up; > > + }; > > + > > + perst-n-pins { > > + pins = "gpio47"; > > + function = "gpio"; > > + drive-strength = <8>; > > + bias-pull-up; > > + output-low; > > + }; > > + > > + wake-n-pins { > > + pins = "gpio48"; > > + function = "pcie1_wake"; > > + drive-strength = <8>; > > + bias-pull-up; > > + }; > > + }; > > +}; > > + > > +&pcie0_phy { > > + status = "okay"; > > +}; > > 'p' < 't', please put this before &tlmm > > Also, would this be something to put into rdp-common? > > Do we still use all of these variants? > > $ ls arch/arm64/boot/dts/qcom/ipq5332-rdp*.dts > arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts > arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts > arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts > arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts Yes. Will fix the comments (here and other patches) and post a new version. Thanks Varada
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 846413817e9a..83eca8435cff 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -62,4 +62,78 @@ data-pins { bias-pull-up; }; }; + + pcie0_default: pcie0-default-state { + clkreq-n-pins { + pins = "gpio37"; + function = "pcie0_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio38"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio39"; + function = "pcie0_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pcie1_default: pcie1-default-state { + clkreq-n-pins { + pins = "gpio46"; + function = "pcie1_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio47"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio48"; + function = "pcie1_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default>; + + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default>; + + perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; + status = "okay"; };