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Thu, 5 Dec 2024 10:28:50 GMT Received: from congzhan2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 5 Dec 2024 02:28:46 -0800 From: Cong Zhang Date: Thu, 5 Dec 2024 18:28:13 +0800 Subject: [PATCH v2] arm64: dts: qcom: sdx75: Correct IRQ number of EL2 non-secure physical timer Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241205-correct_timer_irq-v2-1-7db282a5e475@quicinc.com> X-B4-Tracking: v=1; b=H4sIADyAUWcC/52Ou26DQBBFf8XaOmOxDxbjyv9hWRY7O2tGCaw9E BTL4t8NNGlSpTzFPfe81EDCNKjj7qWEJh449wuYj53CtulvBBwXVqYwTpuiBMwihON15I7kyvK AWJFP6NBrH9Wyuwsl/tmc58vCSXIHYyvU/Jq0qf4wTRo0IDlb1MGXZYinxzcj97jH3K3qlocxy 3Orncx6oJwha2oboaliBBdsDQeyHlwZdLI6HUKhT58kPX3ts9zUWjTZbfrvkss8z2/ADROeOgE AAA== X-Change-ID: 20241205-correct_timer_irq-d7e6fc4c616d To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , Cong Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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In linux, the IRQ number has a fixed 16 offset for PPIs. Therefore, the linux IRQ number of EL2 non-secure physical timer should be 10 (26 - 16). Signed-off-by: Cong Zhang --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- base-commit: bcf2acd8f64b0a5783deeeb5fd70c6163ec5acd7 change-id: 20241205-correct_timer_irq-d7e6fc4c616d Best regards, diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 5f7e59ecf1ca6298cb252ee0654bc7eaeefbd303..b0775173278f3eed0f301b40dfba0f2680d7b0d0 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -1548,6 +1548,6 @@ timer { interrupts = , , , - ; + ; }; };