From patchwork Fri Dec 6 04:31:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13896396 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10373197A77; Fri, 6 Dec 2024 04:33:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733459590; cv=none; b=LQ5gGAVzWlupMybE4M6v0OIsRWAKasTzi6n+VrX0fGgmIDVjsx8dV2ViF1D9gqM82rM+L/tq20OVrVPSHuIjPOMWRMSVsPzB2mLqqpd89LAGDXioGx6GrW6agEIKmvko+IFsYxrDdRK2/7X/KfgIWnyRbms3NYrF9K6qTsdWA/c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733459590; c=relaxed/simple; bh=F5XYfzAOX8/+ObDXYxHiu6kdiwzWLefpqSB+x7049zA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=OWNsphKhh1Rg4bEAd8igiymBGIrbrZC9cQSKFWFrvGWko+Fu+oUaBRhd2penM7n9j25D3Ouh12vBAjZNlf1gestQjNnTBgzDJ3xzCFNZedCUwLWY5mvA6/NAkgGeAnQWz+BPicFEgNSWiZZav7X4d2cKwACifUkM7XePuwXdK00= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Uhu4k7Po; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Uhu4k7Po" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B5HaM36003680; Fri, 6 Dec 2024 04:32:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= zwMdFXyOQUaQ5eFTWFFf1MwDVgU1HWCU3/sWVY5KyX4=; b=Uhu4k7PoLhRO8w7g abIDcPzsnE8VknfNeokPDZOsArO4IrgEM5yOviWIXtG1s6O+M2pnOczjelPd5lsj eZCUGP8PnAuKrwggciG/9fKONby+be+FiVLGM0p9y3KNwn32q2pMDdhwvZlHLtoB qmRGITYERmlHpB3U/wJq4oQ8Xc6qGzjJRBSp3IRSxEHxWtOf8R5VuJc5VPPI2/PA DPNhEB0MDfM0u4jKlQWk9asKMKmqzz52niqal64YwsLq54KEmiGKynPGt/CFnpFN K9irbaCgXovaoWZfuD88wLddaggMncoictlxo4fx6p0oF4A13W7KLv59JCPlqslC vXKsQg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43bbqm29e0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Dec 2024 04:32:28 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B64WRR0016324 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 6 Dec 2024 04:32:27 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 5 Dec 2024 20:32:26 -0800 From: Abhinav Kumar Date: Thu, 5 Dec 2024 20:31:36 -0800 Subject: [PATCH 05/45] drm/msm/dp: add a helper to read mst caps for dp_panel Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241205-dp_mst-v1-5-f8618d42a99a@quicinc.com> References: <20241205-dp_mst-v1-0-f8618d42a99a@quicinc.com> In-Reply-To: <20241205-dp_mst-v1-0-f8618d42a99a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Stephen Boyd , "Chandan Uddaraju" , Guenter Roeck , Kuogee Hsieh , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Vara Reddy , Rob Clark , Tanmay Shah , , , , , , Jessica Zhang , Laurent Pinchart , Abhinav Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733459543; l=2350; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=F5XYfzAOX8/+ObDXYxHiu6kdiwzWLefpqSB+x7049zA=; b=FQLUkaK9BQH2hMvYUzKrmJMkZVQMleI24vXVncP1xnNdmPK1R3soiSnOg7Ilj/D2vO2Dvnkb7 hCt68nE3kOCB3OtSbYaJ2SR6mUBsZySGwKsKN1eSu2gTVqbWcBS0RC0 X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 8QQEOpgFgUYshiV22vjE_0lVezi_ZeGm X-Proofpoint-ORIG-GUID: 8QQEOpgFgUYshiV22vjE_0lVezi_ZeGm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 lowpriorityscore=0 mlxlogscore=999 spamscore=0 adultscore=0 suspectscore=0 malwarescore=0 mlxscore=0 impostorscore=0 bulkscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412060029 Add a helper to check whether a dp_panel is mst capable. Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/dp/dp_aux.h | 1 + drivers/gpu/drm/msm/dp/dp_panel.c | 14 ++++++++++++++ drivers/gpu/drm/msm/dp/dp_panel.h | 1 + 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_aux.h index 39c5b4c8596ab28d822493a6b4d479f5f786cdee..cb97a73cdd6ea74b612053bec578247a42214f23 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.h +++ b/drivers/gpu/drm/msm/dp/dp_aux.h @@ -8,6 +8,7 @@ #include "dp_catalog.h" #include +#include int msm_dp_aux_register(struct drm_dp_aux *msm_dp_aux); void msm_dp_aux_unregister(struct drm_dp_aux *msm_dp_aux); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index d277e9b2cbc03688976b6aa481ee724b186bab51..172de804dec445cb08ad8e3f058407f483cd6684 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -108,6 +108,20 @@ static u32 msm_dp_panel_get_supported_bpp(struct msm_dp_panel *msm_dp_panel, return min_supported_bpp; } +bool msm_dp_panel_read_mst_cap(struct msm_dp_panel *msm_dp_panel) +{ + struct msm_dp_panel_private *panel; + + if (!msm_dp_panel) { + DRM_ERROR("invalid input\n"); + return 0; + } + + panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + + return drm_dp_read_mst_cap(panel->aux, msm_dp_panel->dpcd); +} + int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel, struct drm_connector *connector) { diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 7a38655c443af597c84fb78c6702b2a3ef9822ed..363b416e4cbe290f9c0e6171d6c0c5170f9fea62 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -67,6 +67,7 @@ int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, struct drm_connector *connector); void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel); void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable); +bool msm_dp_panel_read_mst_cap(struct msm_dp_panel *dp_panel); /** * is_link_rate_valid() - validates the link rate