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Thu, 5 Dec 2024 06:54:31 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 437usmedse-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Dec 2024 06:54:31 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4B56sUjP023186; Thu, 5 Dec 2024 06:54:30 GMT Received: from hu-devc-hyd-u20-c-new.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.249]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 4B56sUiD022956 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Dec 2024 06:54:30 +0000 Received: by hu-devc-hyd-u20-c-new.qualcomm.com (Postfix, from userid 3891782) id A4D81213F4; Thu, 5 Dec 2024 12:24:28 +0530 (+0530) From: Mrinmay Sarkar To: manivannan.sadhasivam@linaro.org Cc: quic_shazhuss@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, Mrinmay Sarkar , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Kishon Vijay Abraham I , Bjorn Helgaas , Slark Xiao , Qiang Yu , Mank Wang , Fabio Porcedda , Jeff Johnson , mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v1 1/2] bus: mhi: host: pci_generic: Add supoprt for SA8775P target Date: Thu, 5 Dec 2024 12:24:19 +0530 Message-Id: <20241205065422.2515086-2-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241205065422.2515086-1-quic_msarkar@quicinc.com> References: <20241205065422.2515086-1-quic_msarkar@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 8nz-9oPsdrBhFU7lNLEORKNSdeMurHFj X-Proofpoint-GUID: 8nz-9oPsdrBhFU7lNLEORKNSdeMurHFj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 impostorscore=0 adultscore=0 priorityscore=1501 clxscore=1011 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412050051 Add generic info for SA8775P target. SA8775P supports IP_SW usecase only. Hence use separate configuration to enable IP_SW channel. Signed-off-by: Mrinmay Sarkar --- drivers/bus/mhi/host/pci_generic.c | 34 ++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c index 56ba4192c89c..b62a05e854e9 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -245,6 +245,19 @@ struct mhi_pci_dev_info { .channel = ch_num, \ } +static const struct mhi_channel_config modem_qcom_v2_mhi_channels[] = { + MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 2048, 1), + MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 2048, 2), +}; + +static struct mhi_event_config modem_qcom_v2_mhi_events[] = { + /* first ring is control+data ring */ + MHI_EVENT_CONFIG_CTRL(0, 64), + /* Software channels dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(1, 64), + MHI_EVENT_CONFIG_SW_DATA(2, 64), +}; + static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), @@ -275,6 +288,15 @@ static struct mhi_event_config modem_qcom_v1_mhi_events[] = { MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101) }; +static const struct mhi_controller_config modem_qcom_v3_mhiv_config = { + .max_channels = 128, + .timeout_ms = 8000, + .num_channels = ARRAY_SIZE(modem_qcom_v2_mhi_channels), + .ch_cfg = modem_qcom_v2_mhi_channels, + .num_events = ARRAY_SIZE(modem_qcom_v2_mhi_events), + .event_cfg = modem_qcom_v2_mhi_events, +}; + static const struct mhi_controller_config modem_qcom_v2_mhiv_config = { .max_channels = 128, .timeout_ms = 8000, @@ -294,6 +316,16 @@ static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { .event_cfg = modem_qcom_v1_mhi_events, }; +static const struct mhi_pci_dev_info mhi_qcom_sa8775p_info = { + .name = "qcom-sa8775p", + .edl_trigger = false, + .config = &modem_qcom_v3_mhiv_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32, + .mru_default = 32768, + .sideband_wake = false, +}; + static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = { .name = "qcom-sdx75m", .fw = "qcom/sdx75m/xbl.elf", @@ -720,6 +752,8 @@ static const struct mhi_pci_dev_info mhi_netprisma_fcun69_info = { /* Keep the list sorted based on the PID. New VID should be added as the last entry */ static const struct pci_device_id mhi_pci_id_table[] = { + {PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0116), + .driver_data = (kernel_ulong_t) &mhi_qcom_sa8775p_info }, { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c),