diff mbox series

[v3] clk: qcom: gdsc: Add a flag to skip setting power collapse bits

Message ID 20241205222156.1880299-1-quic_c_gdjako@quicinc.com (mailing list archive)
State New
Headers show
Series [v3] clk: qcom: gdsc: Add a flag to skip setting power collapse bits | expand

Commit Message

Georgi Djakov Dec. 5, 2024, 10:21 p.m. UTC 
The sdm845 platforms have a hardware issue that requires keeping
some of the MMNOC GDSCs in SW collapse mode (which is the power-on
default). But if some driver tries to use these GDSCs and the mode
is updated because of runtime pm calls, we may get a board hang.
Introduce a flag to skip any updates to the power collapse settings
for the impacted GDSCs to avoid unexpected board hangs.

Fixes: 7bb38c20f2b6 ("arm64: dts: qcom: sdm845: Add DT nodes for the TBUs")
Reviewed-by: Mike Tipton <quic_mdtipton@quicinc.com>
Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com>
---
v3:
- No changes

v2: https://lore.kernel.org/r/20241009151657.1041691-1-quic_c_gdjako@quicinc.com/
- Pick up Reviewed-by tag
- Add Fixes tag

v1: https://lore.kernel.org/r/20240813120015.3242787-1-quic_c_gdjako@quicinc.com/ 
 drivers/clk/qcom/gcc-sdm845.c | 6 +++---
 drivers/clk/qcom/gdsc.c       | 3 +++
 drivers/clk/qcom/gdsc.h       | 1 +
 3 files changed, 7 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index dc3aa7014c3e..019b780e31c8 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -3503,7 +3503,7 @@  static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
 		.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
-	.flags = VOTABLE,
+	.flags = VOTABLE | SKIP_SET_COLLAPSE,
 };
 
 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
@@ -3512,7 +3512,7 @@  static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
 		.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
-	.flags = VOTABLE,
+	.flags = VOTABLE | SKIP_SET_COLLAPSE,
 };
 
 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
@@ -3521,7 +3521,7 @@  static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
 		.name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
-	.flags = VOTABLE,
+	.flags = VOTABLE | SKIP_SET_COLLAPSE,
 };
 
 static struct clk_regmap *gcc_sdm670_clocks[] = {
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index fa5fe4c2a2ee..4b83cec9137c 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -121,6 +121,9 @@  static int gdsc_update_collapse_bit(struct gdsc *sc, bool val)
 	u32 reg, mask;
 	int ret;
 
+	if (sc->flags & SKIP_SET_COLLAPSE)
+		return 0;
+
 	if (sc->collapse_mask) {
 		reg = sc->collapse_ctrl;
 		mask = sc->collapse_mask;
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 1e2779b823d1..6bb7e023a19a 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -68,6 +68,7 @@  struct gdsc {
 #define RETAIN_FF_ENABLE	BIT(7)
 #define NO_RET_PERIPH	BIT(8)
 #define HW_CTRL_TRIGGER	BIT(9)
+#define SKIP_SET_COLLAPSE	BIT(10)
 	struct reset_controller_dev	*rcdev;
 	unsigned int			*resets;
 	unsigned int			reset_count;