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Fri, 6 Dec 2024 06:42:10 GMT Received: from jingyw-gv.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 5 Dec 2024 22:42:07 -0800 From: Jingyi Wang Date: Fri, 6 Dec 2024 14:41:13 +0800 Subject: [PATCH] arm64: dts: qcom: qcs8300: Add capacity and DPC properties Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241206-qcs8300_dpc-v1-1-af2e8e6d3da9@quicinc.com> X-B4-Tracking: v=1; b=H4sIAImcUmcC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIxNDIwMz3cLkYgtjA4P4lIJkXSNjgzRzczPzNDMDYyWgjoKi1LTMCrBp0bG 1tQCLi3HAXQAAAA== To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , Jingyi Wang X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733467327; l=2838; i=quic_jingyw@quicinc.com; s=20240910; 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So add it to QCS8300 SoC. Signed-off-by: Jingyi Wang Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) --- base-commit: bcf2acd8f64b0a5783deeeb5fd70c6163ec5acd7 change-id: 20241206-qcs8300_dpc-230f7767f603 Best regards, diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 73abf2ef9c9f..2996b09e4c54 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -44,6 +44,8 @@ cpu0: cpu@0 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd0>; power-domain-names = "psci"; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <472>; l2_0: l2-cache { compatible = "cache"; @@ -61,6 +63,8 @@ cpu1: cpu@100 { next-level-cache = <&l2_1>; power-domains = <&cpu_pd1>; power-domain-names = "psci"; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <472>; l2_1: l2-cache { compatible = "cache"; @@ -78,6 +82,8 @@ cpu2: cpu@200 { next-level-cache = <&l2_2>; power-domains = <&cpu_pd2>; power-domain-names = "psci"; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <507>; l2_2: l2-cache { compatible = "cache"; @@ -95,6 +101,8 @@ cpu3: cpu@300 { next-level-cache = <&l2_3>; power-domains = <&cpu_pd3>; power-domain-names = "psci"; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <507>; l2_3: l2-cache { compatible = "cache"; @@ -112,6 +120,8 @@ cpu4: cpu@10000 { next-level-cache = <&l2_4>; power-domains = <&cpu_pd4>; power-domain-names = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; l2_4: l2-cache { compatible = "cache"; @@ -129,6 +139,8 @@ cpu5: cpu@10100 { next-level-cache = <&l2_5>; power-domains = <&cpu_pd5>; power-domain-names = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; l2_5: l2-cache { compatible = "cache"; @@ -146,6 +158,8 @@ cpu6: cpu@10200 { next-level-cache = <&l2_6>; power-domains = <&cpu_pd6>; power-domain-names = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; l2_6: l2-cache { compatible = "cache"; @@ -163,6 +177,8 @@ cpu7: cpu@10300 { next-level-cache = <&l2_7>; power-domains = <&cpu_pd7>; power-domain-names = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; l2_7: l2-cache { compatible = "cache";