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Wed, 11 Dec 2024 09:36:07 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 01:36:01 -0800 From: Lijuan Gao Date: Wed, 11 Dec 2024 17:35:46 +0800 Subject: [PATCH] arm64: dts: qcom: qcs615: Add CPU capacity and DPC properties Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241211-add_cpu_capacity_and_dpc_properties-v1-1-03aaee023a77@quicinc.com> X-B4-Tracking: v=1; b=H4sIAPFcWWcC/x3NSwrDMAwA0asErWuITUg/VylFKJbSauMIOS0tI XeP6XI2bzao4ioVbt0GLh+tupQW8dRBflF5SlBuDalPQ0wxBmLGbG/MZJR1/SEVRraM5ouJrw0 LFx7HdOZpnvorNMlcZv3+L/fHvh8Wuol6dQAAAA== To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , Lijuan Gao X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733909760; 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They are used to build the energy model, which in turn is used by EAS to take placement decisions. Signed-off-by: Lijuan Gao Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) --- base-commit: 91e71d606356e50f238d7a87aacdee4abc427f07 change-id: 20241211-add_cpu_capacity_and_dpc_properties-8d6627dbfb09 Best regards, diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index c0e4b376a1c6..5d2034a10f2e 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -29,6 +29,8 @@ cpu0: cpu@0 { enable-method = "psci"; power-domains = <&cpu_pd0>; power-domain-names = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&l2_0>; #cooling-cells = <2>; @@ -47,6 +49,8 @@ cpu1: cpu@100 { enable-method = "psci"; power-domains = <&cpu_pd1>; power-domain-names = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&l2_100>; l2_100: l2-cache { @@ -64,6 +68,8 @@ cpu2: cpu@200 { enable-method = "psci"; power-domains = <&cpu_pd2>; power-domain-names = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&l2_200>; l2_200: l2-cache { @@ -81,6 +87,8 @@ cpu3: cpu@300 { enable-method = "psci"; power-domains = <&cpu_pd3>; power-domain-names = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&l2_300>; l2_300: l2-cache { @@ -98,6 +106,8 @@ cpu4: cpu@400 { enable-method = "psci"; power-domains = <&cpu_pd4>; power-domain-names = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&l2_400>; l2_400: l2-cache { @@ -115,6 +125,8 @@ cpu5: cpu@500 { enable-method = "psci"; power-domains = <&cpu_pd5>; power-domain-names = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&l2_500>; l2_500: l2-cache { @@ -132,6 +144,8 @@ cpu6: cpu@600 { enable-method = "psci"; power-domains = <&cpu_pd6>; power-domain-names = "psci"; + capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <404>; next-level-cache = <&l2_600>; #cooling-cells = <2>; @@ -150,6 +164,8 @@ cpu7: cpu@700 { enable-method = "psci"; power-domains = <&cpu_pd7>; power-domain-names = "psci"; + capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <404>; next-level-cache = <&l2_700>; l2_700: l2-cache {