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[5/6] arm64: dts: qcom: correct gpio-ranges for QCS615

Message ID 20241212-correct_gpio_ranges-v1-5-c5f20d61882f@quicinc.com (mailing list archive)
State Superseded
Headers show
Series Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300 | expand

Commit Message

Lijuan Gao Dec. 12, 2024, 9:24 a.m. UTC 
The QCS615 TLMM pin controller has GPIOs 0-122, it also has UFS_RESET
pin for primary UFS memory reset, so correct the gpio-ranges for the UFS
driver can toggle it.

Fixes: 8e266654a2fe ("arm64: dts: qcom: add QCS615 platform")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index c0e4b376a1c6..4c3d8e39ce0b 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -938,7 +938,7 @@  tlmm: pinctrl@3100000 {
 				    "west",
 				    "south";
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
-			gpio-ranges = <&tlmm 0 0 123>;
+			gpio-ranges = <&tlmm 0 0 124>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;