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[6/6] arm64: dts: qcom: correct gpio-ranges for QCS8300

Message ID 20241212-correct_gpio_ranges-v1-6-c5f20d61882f@quicinc.com (mailing list archive)
State Superseded
Headers show
Series Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300 | expand

Commit Message

Lijuan Gao Dec. 12, 2024, 9:24 a.m. UTC 
The QCS8300 TLMM pin controller has GPIOs 0-132, it also has UFS_RESET
pin for primary UFS memory reset, so correct the gpio-ranges for the UFS
driver can toggle it.

Fixes: 7be190e4bdd2 ("arm64: dts: qcom: add QCS8300 platform")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 73abf2ef9c9f..07d6d3ff4365 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -971,7 +971,7 @@  tlmm: pinctrl@f100000 {
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 			gpio-controller;
 			#gpio-cells = <2>;
-			gpio-ranges = <&tlmm 0 0 133>;
+			gpio-ranges = <&tlmm 0 0 134>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			wakeup-parent = <&pdc>;