From patchwork Thu Dec 12 16:23:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohammad Rafi Shaik X-Patchwork-Id: 13905577 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08E7922A7E9; Thu, 12 Dec 2024 16:25:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734020741; cv=none; b=EFip+W+tSrUo1G2t10Bw2weKwZhJkoF3s8WStJESkkeYNmJcXcBT4HXHipZpxab4ZSPmKztQXqWPQw0lC1SOlyzKKcBOd5b819AmEf0gtOQHm5JrLFXWi+cdqEd2s0rcz6WZHoF6A7NFfv5T6oOZqSm41Ro1eINjjsxVasnhOq0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734020741; c=relaxed/simple; bh=EtJNdqCdLTqmX6ETg4G+YzbTDImEI58wItIPOtzsPmA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Bk5v2RC21DOE76hnKY1cXF16NFmd2ghA0gZWkmLOJep9+0BTaZNu36ekCSCJZVsigbQm/KDH9tHhcEkVPrSi1G+1g0Q+6D6jKafiw8My1/dPj2HqQBWgI/Xm/SxEp78jc9Z4BLjPjC3u8M8A2fAq2S1SMAVl/mgFQnwYHFa9U6k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=pOxmLOQy; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="pOxmLOQy" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BCG7L0l002866; Thu, 12 Dec 2024 16:25:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= h3cSWte3E1Zdsl62b8vd86GiM+roAILAjl583zt0Ek0=; b=pOxmLOQy1RkthQqt FgOYLK1VVsKaJGq6fcJhXjNsEqzLBnZnfNRqg3p9Wlko+Fkp72zZu5FbloLj/I0v L4gzV0FVKHpMZtdxSoWtBfGaz6+fpa5TACWCy6cLQQMN7pFith2DaV+Y9G9Q5YlZ dIk3onAmsNV1c6BFuS3zfGeeJy2evkWy36GRBiRLX3B03B50/0tkUXK2M7RJFJwB mnWdlsljuREULWhxADEKchllXMArzSYvH19V9jMYPHdUdvYSKfWuYVlvniVdfhVS Z92UwCnINSaTP4N8psrNOe5qNUC85sX7fjy43PkSXKSwQwTMlBH9LEanXHfZsJ/e 6i+d8w== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43f0r9x1bb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Dec 2024 16:25:24 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BCGPNN1014324 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Dec 2024 16:25:23 GMT Received: from hu-mohs-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 12 Dec 2024 08:25:15 -0800 From: Mohammad Rafi Shaik To: Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Bard Liao , Jaroslav Kysela , "Takashi Iwai" CC: Pierre-Louis Bossart , Sanyog Kale , , , , , , , Mohammad Rafi Shaik Subject: [PATCH v5 3/4] soundwire: qcom: Add set_channel_map api support Date: Thu, 12 Dec 2024 21:53:33 +0530 Message-ID: <20241212162334.36739-4-quic_mohs@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241212162334.36739-1-quic_mohs@quicinc.com> References: <20241212162334.36739-1-quic_mohs@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 6P8Yc_5mmbuFjc5wYAfc3U3Wpy1a-Ehv X-Proofpoint-GUID: 6P8Yc_5mmbuFjc5wYAfc3U3Wpy1a-Ehv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 phishscore=0 spamscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120118 Added qcom_swrm_set_channel_map api to set the master channel mask for TX and RX paths based on the provided slots. Added a new field ch_mask to the qcom_swrm_port_config structure. This field is used to store the master channel mask, which allows more flexible to configure channel mask in runtime for specific active soundwire ports. Modified the qcom_swrm_port_enable function to configure master channel mask. If the ch_mask is set to SWR_INVALID_PARAM or is zero, the function will use the default channel mask. Signed-off-by: Mohammad Rafi Shaik --- drivers/soundwire/qcom.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index e00c5ac496a6..86763ba3a3b2 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -156,6 +156,7 @@ struct qcom_swrm_port_config { u8 word_length; u8 blk_group_count; u8 lane_control; + u8 ch_mask; }; /* @@ -1048,9 +1049,13 @@ static int qcom_swrm_port_enable(struct sdw_bus *bus, { u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); + struct qcom_swrm_port_config *pcfg; u32 val; + pcfg = &ctrl->pconfig[enable_ch->port_num]; ctrl->reg_read(ctrl, reg, &val); + if (pcfg->ch_mask != SWR_INVALID_PARAM && pcfg->ch_mask != 0) + enable_ch->ch_mask = pcfg->ch_mask; if (enable_ch->enable) val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); @@ -1270,6 +1275,27 @@ static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction) return ctrl->sruntime[dai->id]; } +static int qcom_swrm_set_channel_map(struct snd_soc_dai *dai, + unsigned int tx_num, unsigned int *tx_slot, + unsigned int rx_num, unsigned int *rx_slot) +{ + struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); + struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; + int i; + + if (tx_slot) { + for (i = 0; i < tx_num; i++) + ctrl->pconfig[i].ch_mask = tx_slot[i]; + } + + if (rx_slot) { + for (i = 0; i < rx_num; i++) + ctrl->pconfig[i].ch_mask = rx_slot[i]; + } + + return 0; +} + static int qcom_swrm_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { @@ -1306,6 +1332,7 @@ static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = { .shutdown = qcom_swrm_shutdown, .set_stream = qcom_swrm_set_sdw_stream, .get_stream = qcom_swrm_get_sdw_stream, + .set_channel_map = qcom_swrm_set_channel_map, }; static const struct snd_soc_component_driver qcom_swrm_dai_component = {