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Fri, 13 Dec 2024 10:36:22 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 13 Dec 2024 02:36:15 -0800 From: Akhil P Oommen Date: Fri, 13 Dec 2024 16:05:43 +0530 Subject: [PATCH v2 1/4] dt-bindings: display/msm: gpu: Document A612 GPU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241213-qcs615-gpu-dt-v2-1-6606c64f03b5@quicinc.com> References: <20241213-qcs615-gpu-dt-v2-0-6606c64f03b5@quicinc.com> In-Reply-To: <20241213-qcs615-gpu-dt-v2-0-6606c64f03b5@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Bjorn Andersson" CC: , , , , , Akhil P Oommen , <20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0@quicinc.com>, <20241022-qcs615-clock-driver-v4-3-3d716ad0d987@quicinc.com>, <20240924143958.25-2-quic_rlaggysh@quicinc.com>, <20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf@quicinc.com>, <20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624@quicinc.com>, <20241122074922.28153-1-quic_qqzhou@quicinc.com> X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; 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Update the bindings to reflect this. Signed-off-by: Akhil P Oommen --- .../devicetree/bindings/display/msm/gpu.yaml | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 6ddc72fd85b0..1276331cb262 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -217,6 +217,42 @@ allOf: required: - clocks - clock-names + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-612.0 + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + + clock-names: + items: + - const: core + description: GPU Core clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gmu + description: CX GMU clock + - const: xo + description: GPUCC clocksource clock + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_dbgc + + required: + - clocks + - clock-names + else: if: properties: