From patchwork Fri Dec 13 21:33:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeffrey Hugo X-Patchwork-Id: 13907874 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D81C11925BB; Fri, 13 Dec 2024 21:34:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734125653; cv=none; b=LDMdsvpDLFHUYcs/GOUYxChpkmf08ctTlTDezw4lOE0djeE1DnPk9Rd8RLlgSfIV6jG5tLpZh1nw0M7C+4eCmuPvi5RvCd1MFjJBa+12QDNAeVqxv0EH8k8GCms7qYSCHZ/O9y6C91nLdhQ1awnjLUUF1sqv5yF6N7NIsKSwCM4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734125653; c=relaxed/simple; bh=THXTg8tFpMiIDxKGL4VFDDR51qC6Bh2yAWDHq+gj49M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=U/DPVhjeGXSIQgtOu87w50rXidYmVejWRIcB7RDCAKpsnqlBXZXGX03inYX5zAVihvfFcPY1xLve16Immc8TPqLUi8Q+WVpKLDbTXkVGh1tdCqrGGchvoqVoeFuMaRn4KwqduYN18cxcd9qK0KEKxtGeez3fyuarerpymGKkyLA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=NPTO1x5L; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="NPTO1x5L" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BDIJhDp026835; Fri, 13 Dec 2024 21:34:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= PvH8FIvLMMGj4iRucg7GYAoOK96A7mACsCJKpC18frM=; b=NPTO1x5L/tBZONSN lYno7IxUnq/XBd/F0vrbl48lU7I5ZYfCdlDHfijQ/ZeBZEdgC+sylLW8Qh5zDJy+ /ySXqC5tENNCikMNjMWGXg9hd7FD0U850ImOimm1cAaGS3ffpMLa6G/DhoaxGWEH UQpkKe0LKBAZQuy5VjrqfTOKM7RMDhIsBTqbXlTo5M0U5OjYHqLYk3IJNsPoEuv5 g++k7HQjxaNOO6M5NIYlvZV3S0v8c7rtaPDXDcpTT+SCOGwtbW0OtNB3MjaUAKU3 d55xARDH3GFAZzgskXdUzd/t0zIfTrpAmo/EkL1Br8wVB0XTS4Tpm1wcJY4v8sA0 IaS5lg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43fd40qknp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Dec 2024 21:34:06 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BDLY67j024845 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Dec 2024 21:34:06 GMT Received: from jhugo-lnx.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 13 Dec 2024 13:34:05 -0800 From: Jeffrey Hugo To: , , , , CC: , , , , , , Jeffrey Hugo Subject: [PATCH 4/7] accel/qaic: Add support for MSI-X Date: Fri, 13 Dec 2024 14:33:37 -0700 Message-ID: <20241213213340.2551697-5-quic_jhugo@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241213213340.2551697-1-quic_jhugo@quicinc.com> References: <20241213213340.2551697-1-quic_jhugo@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: FmYvfEi25d3qZFJdRW_6iCn8VC2BvuhB X-Proofpoint-ORIG-GUID: FmYvfEi25d3qZFJdRW_6iCn8VC2BvuhB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 suspectscore=0 impostorscore=0 phishscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412130152 From: Youssef Samir AIC200 device will support MSI-X while AIC100 devices will keep using MSI. pci_alloc_irq_vectors() will try to allocate MSI-X vectors if it is supported by the target device, otherwise, it will fallback to MSI. Add support for MSI-X vectors allocation for AIC200 devices. Signed-off-by: Youssef Samir Reviewed-by: Jeffrey Hugo Signed-off-by: Jeffrey Hugo Reviewed-by: Lizhi Hou --- drivers/accel/qaic/qaic_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/accel/qaic/qaic_drv.c b/drivers/accel/qaic/qaic_drv.c index 6e9bed17b3f1..ce0428f6cb82 100644 --- a/drivers/accel/qaic/qaic_drv.c +++ b/drivers/accel/qaic/qaic_drv.c @@ -471,9 +471,9 @@ static int init_msi(struct qaic_device *qdev, struct pci_dev *pdev) int i; /* Managed release since we use pcim_enable_device */ - ret = pci_alloc_irq_vectors(pdev, irq_count, irq_count, PCI_IRQ_MSI); + ret = pci_alloc_irq_vectors(pdev, irq_count, irq_count, PCI_IRQ_MSI | PCI_IRQ_MSIX); if (ret == -ENOSPC) { - ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); + ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX); if (ret < 0) return ret;