From patchwork Tue Dec 17 06:33:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinlong Mao X-Patchwork-Id: 13911179 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EEDB189BA4; Tue, 17 Dec 2024 06:34:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734417243; cv=none; b=WMM+aFRp6iJQrBAXJdfrIZtA2/yrJwsrjEZbiUk/vOWnvu5eROqHPl+0oeTzcAbWqvqfUzETjgvyQNQcF56mUyCgE767mZReD4W7Dy7SnLt8CSx56iC3/xq1HhON7hZcw79ZmtaXw6IhbB6l/H1jJFmu32CmYVXq19BVz0dzxfk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734417243; c=relaxed/simple; bh=5F7VoXGux+CVTPtdcSWN/L7qYtd2g8BLDN1fl+GDKVY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Oea4vY7kwFvXQAIZdi8VG3AV84KtePoFqo1mGW/upFvoAi4j7gPaChvCrK2sigCL6rKzTEKHqLF2nAutSPzYKzF5MYU907qjiU8ostzHpOCOqw9SdJzjMcA2/cRiKuCR8kGj3YI5NwSZHWNUmq905ztgC4b0s9wVuU30+1Kj0/U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Fc+4vtFo; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Fc+4vtFo" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BH58elX017845; Tue, 17 Dec 2024 06:33:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=qcppdkim1; bh=H8UIaiEQDgS4VU32UFd5CA4O cJwkDn4Q+/xqzBocHww=; b=Fc+4vtFoOl9qhdwP6rfSP3ehbgDBEUpOdu8b9DoE IrNRoQiBtf/MHY4l4E0KG765z530vaVfPHpsZ7JVNcCfCm+I7rJwquf/iIs62fgu Z9Es+ioI5Q6oPkaIXdk7FEf+F14K9r4FP9/4Rl3XoHOLluOnAnGhnI+vddyvJkZ+ 6eT2D4MlJzULs2zEtr2EPo0GlspJQ/gauh8rfIXmhy1VxDWgnjkodG9FqoDIomgT DCsqjXLHuvKW7jM7pZOsmWJkxgIjF24vluNmntNeuI1TJphAc6w+IqC2lz80eCzY ylecdv2WY9IXkSCDyZ0LUtdGNxmrB9HUWHsQO3kDFpak8g== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43k2vng6ca-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 06:33:52 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BH6Xpef019973 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 06:33:51 GMT Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 16 Dec 2024 22:33:47 -0800 From: Mao Jinlong To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , "Bjorn Andersson" , Konrad Dybcio CC: Mao Jinlong , , , , , Subject: [PATCH v6 2/2] coresight: Add label sysfs node support Date: Tue, 17 Dec 2024 14:33:24 +0800 Message-ID: <20241217063324.33781-3-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241217063324.33781-1-quic_jinlmao@quicinc.com> References: <20241217063324.33781-1-quic_jinlmao@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 1Y6ENk9yyCZ0V5dni-uZ21Dl40DLCU51 X-Proofpoint-ORIG-GUID: 1Y6ENk9yyCZ0V5dni-uZ21Dl40DLCU51 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 mlxlogscore=999 impostorscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412170052 For some coresight components like CTI and TPDM, there could be numerous of them. From the node name, we can only get the type and register address of the component. We can't identify the HW or the system the component belongs to. Add label sysfs node support for showing the intuitive name of the device. Signed-off-by: Mao Jinlong Reviewed-by: Mike Leach --- .../testing/sysfs-bus-coresight-devices-cti | 6 ++++ .../sysfs-bus-coresight-devices-funnel | 6 ++++ .../testing/sysfs-bus-coresight-devices-tpdm | 6 ++++ drivers/hwtracing/coresight/coresight-sysfs.c | 32 +++++++++++++++++++ 4 files changed, 50 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti index bf2869c413e7..909670e0451a 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti @@ -239,3 +239,9 @@ Date: March 2020 KernelVersion 5.7 Contact: Mike Leach or Mathieu Poirier Description: (Write) Clear all channel / trigger programming. + +What: /sys/bus/coresight/devices//label +Date: Dec 2024 +KernelVersion 6.14 +Contact: Mao Jinlong +Description: (Read) Show hardware context information of device. diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-funnel b/Documentation/ABI/testing/sysfs-bus-coresight-devices-funnel index d75acda5e1b3..944aad879aeb 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-funnel +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-funnel @@ -10,3 +10,9 @@ Date: November 2014 KernelVersion: 3.19 Contact: Mathieu Poirier Description: (RW) Defines input port priority order. + +What: /sys/bus/coresight/devices/.funnel/label +Date: Dec 2024 +KernelVersion 6.14 +Contact: Mao Jinlong +Description: (Read) Show hardware context information of device. diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index bf710ea6e0ef..309802246398 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -257,3 +257,9 @@ Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) /label +Date: Dec 2024 +KernelVersion 6.14 +Contact: Mao Jinlong +Description: (Read) Show hardware context information of device. diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c index a01c9e54e2ed..4af40cd7d75a 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -7,6 +7,7 @@ #include #include #include +#include #include "coresight-priv.h" #include "coresight-trace-id.h" @@ -366,18 +367,47 @@ static ssize_t enable_source_store(struct device *dev, } static DEVICE_ATTR_RW(enable_source); +static ssize_t label_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + + const char *str; + int ret = 0; + + ret = fwnode_property_read_string(dev_fwnode(dev), "label", &str); + if (ret == 0) + return scnprintf(buf, PAGE_SIZE, "%s\n", str); + else + return ret; +} +static DEVICE_ATTR_RO(label); + static struct attribute *coresight_sink_attrs[] = { &dev_attr_enable_sink.attr, + &dev_attr_label.attr, NULL, }; ATTRIBUTE_GROUPS(coresight_sink); static struct attribute *coresight_source_attrs[] = { &dev_attr_enable_source.attr, + &dev_attr_label.attr, NULL, }; ATTRIBUTE_GROUPS(coresight_source); +static struct attribute *coresight_link_attrs[] = { + &dev_attr_label.attr, + NULL, +}; +ATTRIBUTE_GROUPS(coresight_link); + +static struct attribute *coresight_helper_attrs[] = { + &dev_attr_label.attr, + NULL, +}; +ATTRIBUTE_GROUPS(coresight_helper); + const struct device_type coresight_dev_type[] = { [CORESIGHT_DEV_TYPE_SINK] = { .name = "sink", @@ -385,6 +415,7 @@ const struct device_type coresight_dev_type[] = { }, [CORESIGHT_DEV_TYPE_LINK] = { .name = "link", + .groups = coresight_link_groups, }, [CORESIGHT_DEV_TYPE_LINKSINK] = { .name = "linksink", @@ -396,6 +427,7 @@ const struct device_type coresight_dev_type[] = { }, [CORESIGHT_DEV_TYPE_HELPER] = { .name = "helper", + .groups = coresight_helper_groups, } }; /* Ensure the enum matches the names and groups */