From patchwork Thu Dec 19 06:28:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13914521 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3020B21770E; Thu, 19 Dec 2024 06:29:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734589771; cv=none; b=Y02KiA2/JCtf889saaDBpLLNYvRa1mOoHfMfDpFNVyiz7aWDQRop5BA1MV6Kq0P8OuYwY3vIys+gMhbo/2QT+kXUSJOJVOFRm8ee8Kyb+IA54VCyF/FySoK5j/YdOBAa1TEWdTnJapjIVr5CptJ0zajy262FIXInOAwaKE/GOyM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734589771; c=relaxed/simple; bh=TDaLQqBD/BEj8BLWEfEr8Nq3DmdoxtvamkB5mUfEuUs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=r4lPABfE75bzxxhWLpZv29/xc1GD7isUmKVtb1nwBSuDnZu5qhAC7xkRsYwJ1di5Yz+belpf/kWKXJoeS6itxzEt21baBP821XQqfDlbROp6Voe41WaLTHECEPN7Yhr47DkOJ8CpIZ/1HNuHKHRcXv4NFsqydHuGjHn4ouHay88= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Si9X1N3m; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Si9X1N3m" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BIM4KeS029979; Thu, 19 Dec 2024 06:29:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= wbGuWk5VDUOGhd8jBSQEcBeNy2CjtEQs1EjbVQiXuo4=; b=Si9X1N3mT2pQ0qw9 UAmqdOGFfeC1O+JoioFlcPmTTKN/bQuN7JC2h2D5arKDM8QUONpXgzt/2s1Ymu0z Pjj0+RZ80RhZd/CEB8rSOZBJCWnyirNDf8bGpQB3E1YZQkKAOXCegr2DhRIvSk3Y gIHON3yNnH2DPSQZ5TckbjzZBo0bkT0RAAbf9nNCGLcFm9QHv5DEEaqEMv1MPpbk HdE8QKsH6wUuVytbTEs9TaTSKXfnDKWuNCz95B8PsCSDjCc0g80xh5fBhxWlUMwe lKU35HK/S/46GF6MVh9ZJ5Ov20gW577X7+15q6cpwPExrRUPRTt5BHIA4Io1HqOg 7kEhew== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43m6uerwu7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 19 Dec 2024 06:29:22 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BJ6TL2f014431 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 19 Dec 2024 06:29:21 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 18 Dec 2024 22:29:16 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , CC: , Subject: [PATCH v10 4/7] arm64: dts: qcom: ipq5332: Add tsens node Date: Thu, 19 Dec 2024 11:58:36 +0530 Message-ID: <20241219062839.747986-5-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219062839.747986-1-quic_mmanikan@quicinc.com> References: <20241219062839.747986-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: r89tfj94HwUe6FAzxJ4PfclVKkXnTfGI X-Proofpoint-ORIG-GUID: r89tfj94HwUe6FAzxJ4PfclVKkXnTfGI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=948 bulkscore=0 suspectscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 clxscore=1015 impostorscore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412190050 From: Praveenkumar I IPQ5332 has tsens v2.3.3 peripheral. This patch adds the tsens node with nvmem cells for calibration data. Reviewed-by: Konrad Dybcio Signed-off-by: Praveenkumar I Signed-off-by: Manikanta Mylavarapu --- Changes in V10: - Pick up R-b tag - Moved interrupt properties above nvmem arch/arm64/boot/dts/qcom/ipq5332.dtsi | 66 +++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index d3c3e215a15c..4e1668f27d89 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -177,6 +177,46 @@ cpu_speed_bin: cpu-speed-bin@1d { reg = <0x1d 0x2>; bits = <7 2>; }; + + tsens_sens11_off: s11@3a5 { + reg = <0x3a5 0x1>; + bits = <4 4>; + }; + + tsens_sens12_off: s12@3a6 { + reg = <0x3a6 0x1>; + bits = <0 4>; + }; + + tsens_sens13_off: s13@3a6 { + reg = <0x3a6 0x1>; + bits = <4 4>; + }; + + tsens_sens14_off: s14@3ad { + reg = <0x3ad 0x2>; + bits = <7 4>; + }; + + tsens_sens15_off: s15@3ae { + reg = <0x3ae 0x1>; + bits = <3 4>; + }; + + tsens_mode: mode@3e1 { + reg = <0x3e1 0x1>; + bits = <0 3>; + }; + + tsens_base0: base0@3e1 { + reg = <0x3e1 0x2>; + bits = <3 10>; + }; + + tsens_base1: base1@3e2 { + reg = <0x3e2 0x2>; + bits = <5 10>; + }; }; rng: rng@e3000 { @@ -186,6 +226,32 @@ rng: rng@e3000 { clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5332-tsens"; + reg = <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + interrupts = ; + interrupt-names = "combined"; + nvmem-cells = <&tsens_mode>, + <&tsens_base0>, + <&tsens_base1>, + <&tsens_sens11_off>, + <&tsens_sens12_off>, + <&tsens_sens13_off>, + <&tsens_sens14_off>, + <&tsens_sens15_off>; + nvmem-cell-names = "mode", + "base0", + "base1", + "tsens_sens11_off", + "tsens_sens12_off", + "tsens_sens13_off", + "tsens_sens14_off", + "tsens_sens15_off"; + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5332-tlmm"; reg = <0x01000000 0x300000>;