| Message ID | 20241219170011.70140-2-manivannan.sadhasivam@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [1/2] clk: qcom: gcc-sm8550: Do not turn off PCIe GDSCs during gdsc_disable() | expand |
On 19/12/2024 18:00, Manivannan Sadhasivam wrote: > With PWRSTS_OFF_ON, PCIe GDSCs are turned off during gdsc_disable(). This > can happen during scenarios such as system suspend and breaks the resume > of PCIe controllers from suspend. > > So use PWRSTS_RET_ON to indicate the GDSC driver to not turn off the GDSCs > during gdsc_disable() and allow the hardware to transition the GDSCs to > retention when the parent domain enters low power state during system > suspend. > > Cc: stable@vger.kernel.org # 6.8 > Fixes: c58225b7e3d7 ("clk: qcom: add the SM8650 Global Clock Controller driver, part 1") > Reported-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/clk/qcom/gcc-sm8650.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c > index fd9d6544bdd5..9dd5c48f33be 100644 > --- a/drivers/clk/qcom/gcc-sm8650.c > +++ b/drivers/clk/qcom/gcc-sm8650.c > @@ -3437,7 +3437,7 @@ static struct gdsc pcie_0_gdsc = { > .pd = { > .name = "pcie_0_gdsc", > }, > - .pwrsts = PWRSTS_OFF_ON, > + .pwrsts = PWRSTS_RET_ON, > .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, > }; > > @@ -3448,7 +3448,7 @@ static struct gdsc pcie_0_phy_gdsc = { > .pd = { > .name = "pcie_0_phy_gdsc", > }, > - .pwrsts = PWRSTS_OFF_ON, > + .pwrsts = PWRSTS_RET_ON, > .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, > }; > > @@ -3459,7 +3459,7 @@ static struct gdsc pcie_1_gdsc = { > .pd = { > .name = "pcie_1_gdsc", > }, > - .pwrsts = PWRSTS_OFF_ON, > + .pwrsts = PWRSTS_RET_ON, > .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, > }; > > @@ -3470,7 +3470,7 @@ static struct gdsc pcie_1_phy_gdsc = { > .pd = { > .name = "pcie_1_phy_gdsc", > }, > - .pwrsts = PWRSTS_OFF_ON, > + .pwrsts = PWRSTS_RET_ON, > .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, > }; > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on QRD8650
diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c index fd9d6544bdd5..9dd5c48f33be 100644 --- a/drivers/clk/qcom/gcc-sm8650.c +++ b/drivers/clk/qcom/gcc-sm8650.c @@ -3437,7 +3437,7 @@ static struct gdsc pcie_0_gdsc = { .pd = { .name = "pcie_0_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, + .pwrsts = PWRSTS_RET_ON, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, }; @@ -3448,7 +3448,7 @@ static struct gdsc pcie_0_phy_gdsc = { .pd = { .name = "pcie_0_phy_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, + .pwrsts = PWRSTS_RET_ON, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, }; @@ -3459,7 +3459,7 @@ static struct gdsc pcie_1_gdsc = { .pd = { .name = "pcie_1_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, + .pwrsts = PWRSTS_RET_ON, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, }; @@ -3470,7 +3470,7 @@ static struct gdsc pcie_1_phy_gdsc = { .pd = { .name = "pcie_1_phy_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, + .pwrsts = PWRSTS_RET_ON, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, };
With PWRSTS_OFF_ON, PCIe GDSCs are turned off during gdsc_disable(). This can happen during scenarios such as system suspend and breaks the resume of PCIe controllers from suspend. So use PWRSTS_RET_ON to indicate the GDSC driver to not turn off the GDSCs during gdsc_disable() and allow the hardware to transition the GDSCs to retention when the parent domain enters low power state during system suspend. Cc: stable@vger.kernel.org # 6.8 Fixes: c58225b7e3d7 ("clk: qcom: add the SM8650 Global Clock Controller driver, part 1") Reported-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/clk/qcom/gcc-sm8650.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)