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Mon, 13 Jan 2025 21:26:46 GMT Received: from hu-molvera-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 13 Jan 2025 13:26:46 -0800 From: Melody Olvera Date: Mon, 13 Jan 2025 13:26:43 -0800 Subject: [PATCH 4/4] arm64: dts: qcom: sm8750: Add LLCC node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250113-sm8750_llcc_master-v1-4-5389b92e2d7a@quicinc.com> References: <20250113-sm8750_llcc_master-v1-0-5389b92e2d7a@quicinc.com> In-Reply-To: <20250113-sm8750_llcc_master-v1-0-5389b92e2d7a@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Satya Durga Srinivasu Prabhala , Trilok Soni CC: , , , Melody Olvera X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736803604; l=1173; i=quic_molvera@quicinc.com; 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Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..3cd7b40bdde68ac00c3dbe7fb3f20ebb2ba27045 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2888,6 +2888,17 @@ gem_noc: interconnect@24100000 { #interconnect-cells = <2>; }; + cache-controller@24800000 { + compatible = "qcom,sm8750-llcc"; + reg = <0x0 0x24800000 0x0 0x200000>, <0x0 0x25800000 0x0 0x200000>, + <0x0 0x24C00000 0x0 0x200000>, <0x0 0x25C00000 0x0 0x200000>, + <0x0 0x26800000 0x0 0x200000>, <0x0 0x26C00000 0x0 0x200000>; + reg-names = "llcc0_base", "llcc1_base", + "llcc2_base", "llcc3_base", + "llcc_broadcast_base", "llcc_broadcast_and_base"; + interrupts = ; + }; + nsp_noc: interconnect@320c0000 { compatible = "qcom,sm8750-nsp-noc"; reg = <0x0 0x320c0000 0x0 0x13080>;