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Wed, 15 Jan 2025 09:32:07 GMT Received: from hu-renjiang-sha.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 15 Jan 2025 01:32:04 -0800 From: Renjiang Han Date: Wed, 15 Jan 2025 15:00:53 +0530 Subject: [PATCH v3 2/3] venus: pm_helpers: Use dev_pm_genpd_set_hwmode to switch GDSC mode on V4 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250115-switch_gdsc_mode-v3-2-9a24d2fd724c@quicinc.com> References: <20250115-switch_gdsc_mode-v3-0-9a24d2fd724c@quicinc.com> In-Reply-To: <20250115-switch_gdsc_mode-v3-0-9a24d2fd724c@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Stanimir Varbanov , Vikash Garodia , Bryan O'Donoghue , Mauro Carvalho Chehab CC: , , , , Renjiang Han X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736933518; l=2837; i=quic_renjiang@quicinc.com; s=20241001; h=from:subject:message-id; bh=+/6ymI2gxodvy4p0D6VcTcHJuB8emEerX+YHB0Wuy38=; b=rHPzVm2FIctSOKUUsQMuWvvdVy/iq3ErV3mnCIlZY5yciExfM3skxjrzcZrxO5O3Btm9w8JcC WBheyKji5oOCiBw6aGyHJENLUqwhNXVWU2VinDfGd+t6oDanyzcT6wa X-Developer-Key: i=quic_renjiang@quicinc.com; a=ed25519; pk=8N59kMJUiVH++5QxJzTyHB/wh/kG5LxQ44j9zhUvZmw= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: p2y_YRdd2eFDnqC_cuZPJhhHNfC7PK2d X-Proofpoint-GUID: p2y_YRdd2eFDnqC_cuZPJhhHNfC7PK2d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-15_03,2025-01-15_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 phishscore=0 spamscore=0 clxscore=1015 mlxscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501150072 The POWER_CONTROL register addresses are not constant and can vary across the variants. Also as per the HW recommendation, the GDSC mode switching needs to be controlled from respective GDSC register and this is a uniform approach across all the targets. Hence use dev_pm_genpd_set_hwmode() API which controls GDSC mode switching using its respective GDSC register. In venus v4 variants, the vcodec gdsc gets enabled in SW mode by default with new HW_CTRL_TRIGGER flag and there is no need to switch it to SW mode again after enable, hence add check to avoid switching gdsc to SW mode again after gdsc enable. Similarly add check to avoid switching GDSC to HW mode before disabling the GDSC, so GDSC gets enabled in SW mode in the next enable. Signed-off-by: Renjiang Han --- drivers/media/platform/qcom/venus/pm_helpers.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/qcom/venus/pm_helpers.c b/drivers/media/platform/qcom/venus/pm_helpers.c index 33a5a659c0ada0ca97eebb5522c5f349f95c49c7..a2062b366d4aedba3eb5e4be456a005847eaec0b 100644 --- a/drivers/media/platform/qcom/venus/pm_helpers.c +++ b/drivers/media/platform/qcom/venus/pm_helpers.c @@ -412,7 +412,7 @@ static int vcodec_control_v4(struct venus_core *core, u32 coreid, bool enable) u32 val; int ret; - if (IS_V6(core)) + if (IS_V6(core) || IS_V4(core)) return dev_pm_genpd_set_hwmode(core->pmdomains->pd_devs[coreid], !enable); else if (coreid == VIDC_CORE_ID_1) { ctrl = core->wrapper_base + WRAPPER_VCODEC0_MMCC_POWER_CONTROL; @@ -450,7 +450,7 @@ static int poweroff_coreid(struct venus_core *core, unsigned int coreid_mask) vcodec_clks_disable(core, core->vcodec0_clks); - if (!IS_V6(core)) { + if (!IS_V6(core) && !IS_V4(core)) { ret = vcodec_control_v4(core, VIDC_CORE_ID_1, false); if (ret) return ret; @@ -468,7 +468,7 @@ static int poweroff_coreid(struct venus_core *core, unsigned int coreid_mask) vcodec_clks_disable(core, core->vcodec1_clks); - if (!IS_V6(core)) { + if (!IS_V6(core) && !IS_V4(core)) { ret = vcodec_control_v4(core, VIDC_CORE_ID_2, false); if (ret) return ret; @@ -491,7 +491,7 @@ static int poweron_coreid(struct venus_core *core, unsigned int coreid_mask) if (ret < 0) return ret; - if (!IS_V6(core)) { + if (!IS_V6(core) && !IS_V4(core)) { ret = vcodec_control_v4(core, VIDC_CORE_ID_1, true); if (ret) return ret; @@ -511,7 +511,7 @@ static int poweron_coreid(struct venus_core *core, unsigned int coreid_mask) if (ret < 0) return ret; - if (!IS_V6(core)) { + if (!IS_V6(core) && !IS_V4(core)) { ret = vcodec_control_v4(core, VIDC_CORE_ID_2, true); if (ret) return ret;