@@ -53,6 +53,30 @@ &dwc_1 {
dr_mode = "host";
};
+&pcie2 {
+ pinctrl-0 = <&pcie2_default_state>;
+ pinctrl-names = "default";
+
+ perst-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie2_phy {
+ status = "okay";
+};
+
+&pcie3 {
+ pinctrl-0 = <&pcie3_default_state>;
+ pinctrl-names = "default";
+
+ perst-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie3_phy {
+ status = "okay";
+};
+
&qusb_phy_0 {
vdd-supply = <&vreg_misc_0p925>;
vdda-pll-supply = <&vreg_misc_1p8>;
@@ -147,6 +171,22 @@ data-pins {
bias-pull-up;
};
};
+
+ pcie2_default_state: pcie2-default-state {
+ pins = "gpio31";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-low;
+ };
+
+ pcie3_default_state: pcie3-default-state {
+ pins = "gpio34";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-low;
+ };
};
&uart1 {
@@ -166,4 +206,3 @@ &usb3 {
&xo_board {
clock-frequency = <24000000>;
};
-
Enable the PCIe controller and PHY nodes corresponding to RDP466. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> --- Changes in V2: - Drop the inner wrapper in pcie2_default_state and pcie3_default_state nodes. - Reordered the pcie nodes. arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 41 ++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-)