From patchwork Wed Jan 15 10:30:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 13940262 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF5D01E9914; Wed, 15 Jan 2025 10:31:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736937099; cv=none; b=ChYaQWtVSLc5rPRwUkGOnjb1L7B/0Waiqw7dvCUyG2jkpC88fe9nTGedMmz/7rH92WGpzwNGU24QFulBX37nDRfsuy7vSt+o/nra5gcP0YQPwcRm8Ccs9nLUHCop04q0vIkuuYhsav9MJh9XndaNaqOOg8oJELvDrgak7DOcgkA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736937099; c=relaxed/simple; bh=QcuJlwowsfElt3102PL0P3iKOTannpbKw8plW4NdhUo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HIYErtpzUsHRYrf8uA50HAuteAjyk7CWV2F8rMWaVgrGD//KX+5f4/iQ6Ti6kfEilhJqBXJt5JvBdK3jQ8+Jno0qvkEupBQRPqloK7pkjySWJX36Ekix+Ck7WVHNDRrXJ43n/YXULXBpMZDXMqf/TEpC/d8LyhEidxOPe/lVqLM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=XI2R2KlX; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="XI2R2KlX" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50F2rYWp019768; Wed, 15 Jan 2025 10:31:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= nnrDNEhr0H/NPGw3b/3KDb8NCfjDYBFGyVH2aj4nZhw=; b=XI2R2KlXyli/Xmkg R/1ZGB/yaKjzcYwl/43n1l6M5UIdAmt3OV/e63vlnJ3EOS1yrxpB5Jbvc7gm7VUf xBe8UoPyToQv/rvVd6+MwddeDT4RQiyzpsIruBaB0hyxmGirE82AWIqFxVVYQuAz BRWaaFNml/BV88hYwdKNhfN12HYfJ+xRGkEBCHrQz99T0MvSKF6/0pUg2VnL4goD GBZMEttYaT+sb4EIA3rDP+hpYQW5OqmswJIn1SYOMukEncBZJwAJrw1Wv229nek7 oJxlzO5mMdueACUDdGwmjtFEAudIuhQ3kehKXKVfDgScdZRYdZzpT1ZIWlu0vvvs WcSxxQ== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4464mts11w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Jan 2025 10:31:28 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50FAVRjt005321 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Jan 2025 10:31:27 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 15 Jan 2025 02:31:22 -0800 From: Md Sadre Alam To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v6 11/12] crypto: qce - Add support for lock/unlock in sha Date: Wed, 15 Jan 2025 16:00:03 +0530 Message-ID: <20250115103004.3350561-12-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250115103004.3350561-1-quic_mdalam@quicinc.com> References: <20250115103004.3350561-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: dEEELatXcjlXVYLTMvYXw6Mt5D0jmMI0 X-Proofpoint-GUID: dEEELatXcjlXVYLTMvYXw6Mt5D0jmMI0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-15_04,2025-01-15_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501150079 Add support for lock/unlock on bam pipe in sha. If multiple EE's(Execution Environment) try to access the same crypto engine then before accessing the crypto engine EE's has to lock the bam pipe and then submit the request to crypto engine. Once request done then EE's has to unlock the bam pipe so that others EE's can access the crypto engine. Signed-off-by: Md Sadre Alam --- Change in [v6] * No change Change in [v5] * No change Change in [v4] * No change Change in [v3] * Move qce_bam_release_lock() after qca_dma_terminate_all() api Change in [v2] * Added qce_bam_acquire_lock() and qce_bam_release_lock() api for SHA Change in [v1] * This patch was not included in [v1] drivers/crypto/qce/sha.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c index 71b748183cfa..e495703031b3 100644 --- a/drivers/crypto/qce/sha.c +++ b/drivers/crypto/qce/sha.c @@ -60,6 +60,8 @@ static void qce_ahash_done(void *data) rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]); rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]); + qce_bam_release_lock(qce); + error = qce_check_status(qce, &status); if (error < 0) dev_dbg(qce->dev, "ahash operation error (%x)\n", status); @@ -90,6 +92,8 @@ static int qce_ahash_async_req_handle(struct crypto_async_request *async_req) rctx->authklen = AES_KEYSIZE_128; } + qce_bam_acquire_lock(qce); + rctx->src_nents = sg_nents_for_len(req->src, req->nbytes); if (rctx->src_nents < 0) { dev_err(qce->dev, "Invalid numbers of src SG.\n");