From patchwork Fri Jan 17 16:00:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13943490 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11ADE1A23A8 for ; Fri, 17 Jan 2025 16:02:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737129737; cv=none; b=jozz/Ej0xPTnLOXaBwh98S7nYzUd4haDe6o4sdb9EJdntbykrcL1IhZ4Vc/RA6sJLvAmUbeyYu3tryILkAMWB1w5ED54Q95sOKEClUxheCZx/9CCtp0nw9K956+I+umefkUmdwu3pp7jRo7vf4FV/FVQsWH56lqwwGcmUxqDPoI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737129737; c=relaxed/simple; bh=sUuICZ08SQSbhFJWF/1DzEd5meA+YJyjVUzug+zCHWE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ohvcMKAiPIMVyJwKE1WjlYAseg+VlccTPiWcsBmD6rh/pW5TE63ovhSpOe8Ov2AaTm9FerBx2QNuLSGjXTbI3dlU2YXZQizadA5sP2lH1Ip9LRNf/aiKDIRH0hGV7JGS8tnke5la/PagdheD48+SqhLjCQ2B6BRDgImEEoyqI6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=fiC0zwsG; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fiC0zwsG" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-21661be2c2dso45398735ad.1 for ; Fri, 17 Jan 2025 08:02:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737129735; x=1737734535; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3un6sz4f2PupjIWaHPEgPdfQGOWacFMdRr0Cl0n4d1Y=; b=fiC0zwsGjL4cOEbzLxf1KlttcmjJOidBy3T05LjFAtIcQ02fjsDPivPAvr3C/rim0S VAMWF7y3zA8mN1Z9ydwhygVPABOzshcfiRcAqxoJBIS2jWk72GqI9klahRrQ5pS1uPFw NxU95OW5Gcq+dpMrIoG9CQV05LgLHD314MbE5TBXjltPQHrFvPH0gEKQ3ai+/ga3NyqW 7zO03hqDu2o7shB9skqvz7cm1bR/QW4Yiai23eItb6mmUlQHoZgsCWo8ugZ+dlNy3PY6 frJpb+1Yzc8AIAdD+3AvcrSnOD0YUnT3K/Dr0HiGD3YHBC8Au/DtzmNvZw7U7fZ2jFFK bbCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737129735; x=1737734535; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3un6sz4f2PupjIWaHPEgPdfQGOWacFMdRr0Cl0n4d1Y=; b=wrMQq0/NkFZ1WTfFk9L76BMG+khhAzaUl+TqH6TFLmLywr8CiHzBRNQpQ0L4srKF6X rYoXdbMQVj9SyGGualmZJSvmLTLT4khQ6KLz0hPcStNxWnOj9sV/tB8amXkJ8BwKABwY nzgHyGTumD13ar3R3lifXZnZHz2v4lR+FZYYWqrRhPHP+aYmo6Cso+J9jWd7EdIMYh9C oWHDdEJi/B/+lrO+qq1goyJG6PKiYgsx694In6ogoj5UZAbxdGFR6O54YSKuk/oVkaNA MgsFPzj+Ef+aqIofj9oRGKtoZCYN7mkO1aPU4R8Duov6zIzfRKhtx9+S5KqlBJpM3ZK8 20PQ== X-Gm-Message-State: AOJu0YzMlXufi46J53I7xjwSvLxRfNEOY46QGAXfZXU30TQ+zHmKKEhu Kfvu8ZThT0PkOaKn6S35jj5hffGYqpJB8fC495xUqeJuOa0y5S/ZGwuwW1F42QM= X-Gm-Gg: ASbGncun02iAC1NOzdh2Nxsc1IWloVvW1P/Ts+TUFoUICA59+smFir32WA+tryJjFiT Eca09IZHeWmDoXeEzRfBVEFMslvV2vpL6467EiiK/khEnRipZ6p7Q2fCZQEQHes+b7TJ+PBqKgO Gy+p+YEWo8Qrun4uMoP2iXHXjRd8yUVm1DKPL0X+P/0HuKt6qtr6dwPcGqCjdDIw6kTc3kmzJeW NbSF/HTl4ZRWxAHSBDjed9RubaZRR4n7myiNPXUCgMCZcW45H67Tw== X-Google-Smtp-Source: AGHT+IEoYOqoDMGqHsHLXSSjrfXVeQ6tiv8sPdBfHOPA8lvbIc/Bvjl+QdbCCVHAtTM9ZGbbTXGvJg== X-Received: by 2002:a17:902:f690:b0:216:4348:149d with SMTP id d9443c01a7336-21c356228a8mr48342905ad.53.1737129735514; Fri, 17 Jan 2025 08:02:15 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21c2d3e0df9sm17879755ad.196.2025.01.17.08.02.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 08:02:15 -0800 (PST) From: Jun Nie Date: Sat, 18 Jan 2025 00:00:54 +0800 Subject: [PATCH v5 11/15] drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-11-9701a16340da@linaro.org> References: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-0-9701a16340da@linaro.org> In-Reply-To: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-0-9701a16340da@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1737129659; l=4903; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=sUuICZ08SQSbhFJWF/1DzEd5meA+YJyjVUzug+zCHWE=; b=XMbzeZ8vKLkKszBj/CrueBgL0Rn9VV3nlJqpBrI8X2Qr+d3eeKrtKvJxNGN0iMHtCLtGLuO5G ei8Uefp5jusDS1BPbHodcm0nC59purvp0tOndC1NucQCxwsVwps4yL4 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= The stage contains configuration for a mixer pair. Currently the plane supports just one stage and 2 pipes. Quad-pipe support will require handling 2 stages and 4 pipes at the same time. In preparation for that add a separate define, PIPES_PER_PLANE, to denote number of pipes that can be used by the plane. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 14 +++++++------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 ++-- 4 files changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 193818b02197d..81474823e6799 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -463,7 +463,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable = true; - for (i = 0; i < PIPES_PER_STAGE; i++) { + for (i = 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; set_bit(pstate->pipe[i].sspp->idx, fetch_active); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index ba7bb05efe9b8..5f010d36672cc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -34,6 +34,7 @@ #define DPU_MAX_PLANES 4 #endif +#define PIPES_PER_PLANE 2 #define PIPES_PER_STAGE 2 #ifndef DPU_MAX_DE_CURVES #define DPU_MAX_DE_CURVES 3 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index ef44af5ab681c..d67f2ad20b475 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1078,7 +1078,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, * resources are freed by dpu_crtc_assign_plane_resources(), * but clean them here. */ - for (i = 0; i < PIPES_PER_STAGE; i++) + for (i = 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp = NULL; return 0; @@ -1129,7 +1129,7 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, pipe_cfg = &pstate->pipe_cfg[0]; r_pipe_cfg = &pstate->pipe_cfg[1]; - for (i = 0; i < PIPES_PER_STAGE; i++) + for (i = 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp = NULL; if (!plane_state->fb) @@ -1241,7 +1241,7 @@ void dpu_plane_flush(struct drm_plane *plane) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); else { - for (i = 0; i < PIPES_PER_STAGE; i++) + for (i = 0; i < PIPES_PER_PLANE; i++) dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); } @@ -1364,7 +1364,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane, &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); /* move the assignment here, to ease handling to another pairs later */ - for (i = 0; i < PIPES_PER_STAGE; i++) { + for (i = 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], @@ -1378,7 +1378,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane, pstate->plane_fetch_bw = 0; pstate->plane_clk = 0; - for (i = 0; i < PIPES_PER_STAGE; i++) { + for (i = 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, @@ -1397,7 +1397,7 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane) struct dpu_sw_pipe *pipe; int i; - for (i = 0; i < PIPES_PER_STAGE; i += 1) { + for (i = 0; i < PIPES_PER_PLANE; i += 1) { pipe = &pstate->pipe[i]; if (!pipe->sspp) continue; @@ -1519,7 +1519,7 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p, drm_printf(p, "\tstage=%d\n", pstate->stage); - for (i = 0; i < PIPES_PER_STAGE; i++) { + for (i = 0; i < PIPES_PER_PLANE; i++) { pipe = &pstate->pipe[i]; if (!pipe->sspp) continue; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 052fd046e8463..18ff5ec2603ed 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -33,8 +33,8 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; - struct dpu_sw_pipe pipe[PIPES_PER_STAGE]; - struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE]; + struct dpu_sw_pipe pipe[PIPES_PER_PLANE]; + struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE]; enum dpu_stage stage; bool needs_qos_remap; bool pending;