Message ID | 20250119-qcs615-mm-v4-clockcontroller-v4-10-5d1bdb5a140c@quicinc.com (mailing list archive) |
---|---|
State | New |
Headers | show
Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18E701DE8A0; Sun, 19 Jan 2025 10:24:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737282255; cv=none; b=b2b4rePyyiXurhr5VpKFo9uyrs2D4uoHh7tK8BuYQGn/7QWLnR10Z8i8bf1VY3B71IhBSBRxMisTpE1IQKdIpq9awnVEsnohoKbBPV+ZwalcoHpTWwCvuL/W1BF9hnCd64HnfmwNZtKPC3ffz3tNaRDUyTQDfDAvRoc0aTPkp9w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737282255; c=relaxed/simple; bh=hrqMq79tYF7/R1WujiAawYIvE3BKCVoDQJQuBcoTvxA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=dv28vcM8uQ4hygWHr9E6lZVd1dMCGLlsUtvqEn6DLOeLNL2JkxqgX0ThMv7yWlIMcN76fYD4PqBsNQtOAYO8QUwB+AF+NVr2/8U1uNgXjWYwX99WvLxOPCt51SgUEIqVkySCyXaLPn7UCDTH2SFwpb7J9jDQbEsX01n7Ng/scMY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=i8BjDwyU; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="i8BjDwyU" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50J4e246031842; Sun, 19 Jan 2025 10:24:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 0WgwbtnjjC8UOSTl+bIq40/lkigMUOhRfKHrFb56AsM=; b=i8BjDwyUSKkpsRJo aoIQdlTYcaTXgEefu2TRKGe0oC5DRBP1BZ3UUwu6BCpMFhBJEp2A29VVh5y6s3LU akUQ6SNDey5v4I/5MTmAksN6i7HyDGdA4aBoWHMm8S8TzFb/ix7D1TGeB+f6Qxd/ UCtKbkbEnIKzzk0yd/elXlElbYd8ETyI6z5wOjmgws5h0qz6XGYLFhumjCpEyAFQ 6a32VhGKnOrQBqdYeSaBl+N2CXsewsRDk2aI0eH2k9tJvNYlNnG4jwpm3UxuU+aC J+PDmMvo8eZRSpe/F4H+NU53VKvu32rIKsUg92ZB6EMFZtHFfcgeLDJ6blj+vnuK zy+L2Q== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44838qsyb2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 19 Jan 2025 10:24:05 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50JAO4nP017397 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 19 Jan 2025 10:24:04 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 19 Jan 2025 02:23:59 -0800 From: Taniya Das <quic_tdas@quicinc.com> Date: Sun, 19 Jan 2025 15:53:04 +0530 Subject: [PATCH v4 10/10] arm64: defconfig: Enable QCS615 clock controllers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20250119-qcs615-mm-v4-clockcontroller-v4-10-5d1bdb5a140c@quicinc.com> References: <20250119-qcs615-mm-v4-clockcontroller-v4-0-5d1bdb5a140c@quicinc.com> In-Reply-To: <20250119-qcs615-mm-v4-clockcontroller-v4-0-5d1bdb5a140c@quicinc.com> To: Bjorn Andersson <andersson@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org> CC: Ajit Pandey <quic_ajipan@quicinc.com>, Imran Shaik <quic_imrashai@quicinc.com>, Jagadeesh Kona <quic_jkona@quicinc.com>, <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, Taniya Das <quic_tdas@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: b4iK6c6bIIR31ZxDvKyd1BuorbNMe5Z- X-Proofpoint-GUID: b4iK6c6bIIR31ZxDvKyd1BuorbNMe5Z- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-18_10,2025-01-16_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 adultscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=719 clxscore=1015 spamscore=0 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501190086 |
Series |
Add support for videocc, camcc, dispcc and gpucc on Qualcomm QCS615 platform
|
expand
|
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 246a13412bf05221e4e306ff0857dde13f0fd155..3f43d09c78e82c95dded55ef3f2eabb1ee2579c1 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1341,11 +1341,15 @@ CONFIG_MSM_GCC_8998=y CONFIG_MSM_MMCC_8998=m CONFIG_QCM_GCC_2290=y CONFIG_QCM_DISPCC_2290=m +CONFIG_QCS_DISPCC_615=m +CONFIG_QCS_CAMCC_615=m CONFIG_QCS_GCC_404=y CONFIG_QCS_GCC_615=y CONFIG_QCS_GCC_8300=y CONFIG_SC_CAMCC_7280=m CONFIG_SA_CAMCC_8775P=m +CONFIG_QCS_GPUCC_615=m +CONFIG_QCS_VIDEOCC_615=m CONFIG_QDU_GCC_1000=y CONFIG_SC_CAMCC_8280XP=m CONFIG_SC_DISPCC_7280=m