| Message ID | 20250211-b4-branch-gfx-smmu-v5-2-ff0bcb6a3c51@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for GPU SMMU on QCS8300 | expand |
On 11/02/2025 05:45, Pratyush Brahma wrote: > Add the device node for gfx smmu that is required for gpu > specific address translations. > > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 39 +++++++++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) As pointed out by Rob, this wasn't ever tested. One more example of work where you have the binding in the same patch but refuse to use it. NAK Best regards, Krzysztof
On 2/12/2025 10:09 AM, Pratyush Brahma wrote: > > > On 2/11/2025 8:45 PM, Krzysztof Kozlowski wrote: >> On 11/02/2025 05:45, Pratyush Brahma wrote: >>> Add the device node for gfx smmu that is required for gpu >>> specific address translations. >>> >>> Signed-off-by: Pratyush Brahma<quic_pbrahma@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 39 +++++++++++++++++++++++++++++++++++ >>> 1 file changed, 39 insertions(+) >> As pointed out by Rob, this wasn't ever tested. One more example of work >> where you have the binding in the same patch but refuse to use it. No, I had tested these patches against the dt_bindings_check and didn't see these errors. It seems I need to upgrade my dtschema as Rob pointed out, reorder the clocks and resend. However, I guess I need to update the clock list in the bindings file as per the order suggested by Konrad in version 3. >> NAK >> >> Best regards, >> Krzysztof > -- > Thanks and Regards > Pratyush Brahma
On 12/02/2025 06:19, Pratyush Brahma wrote: > > On 2/12/2025 10:09 AM, Pratyush Brahma wrote: >> >> >> On 2/11/2025 8:45 PM, Krzysztof Kozlowski wrote: >>> On 11/02/2025 05:45, Pratyush Brahma wrote: >>>> Add the device node for gfx smmu that is required for gpu >>>> specific address translations. >>>> >>>> Signed-off-by: Pratyush Brahma<quic_pbrahma@quicinc.com> >>>> --- >>>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 39 +++++++++++++++++++++++++++++++++++ >>>> 1 file changed, 39 insertions(+) >>> As pointed out by Rob, this wasn't ever tested. One more example of work >>> where you have the binding in the same patch but refuse to use it. > No, I had tested these patches against the dt_bindings_check and didn't > see these errors. > It seems I need to upgrade my dtschema as Rob pointed out, reorder the > clocks and resend. The reported errors are not relevant at all to upgraded or not upgraded dtschema. This just wasn't tested. > Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 4a057f7c0d9fae0ebd1b3cf3468746b382bc886b..f1c90db7b0e689035fbbaaa551611be34adf9ab6 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -2674,6 +2674,45 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x3da0000 0x0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + + clock-names = "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hub_aon_clk"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + pmu@9091000 { compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0x0 0x9091000 0x0 0x1000>;
Add the device node for gfx smmu that is required for gpu specific address translations. Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 39 +++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)