| Message ID | 20250213-a623-gpu-support-v1-2-993c65c39fd2@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | EDITME: Support for Adreno 623 GPU | expand |
On Thu, Feb 13, 2025 at 09:40:07PM +0530, Akhil P Oommen wrote: > From: Jie Zhang <quic_jiezh@quicinc.com> > > Add support for Adreno 623 GPU found in QCS8300 chipsets. > > Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +++++++++++++++++++++++++++++ > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ > drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > 4 files changed, 43 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index edffb7737a97..ac156c8b5af9 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -879,6 +879,35 @@ static const struct adreno_info a6xx_gpus[] = { > { 0, 0 }, > { 137, 1 }, > ), > + }, { > + .chip_ids = ADRENO_CHIP_IDS(0x06020300), > + .family = ADRENO_6XX_GEN3, > + .fw = { > + [ADRENO_FW_SQE] = "a650_sqe.fw", > + [ADRENO_FW_GMU] = "a623_gmu.bin", > + }, > + .gmem = SZ_512K, > + .inactive_period = DRM_MSM_INACTIVE_PERIOD, > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | > + ADRENO_QUIRK_HAS_HW_APRIV, > + .init = a6xx_gpu_init, > + .a6xx = &(const struct a6xx_info) { > + .hwcg = a620_hwcg, > + .protect = &a650_protect, > + .gmu_cgc_mode = 0x00020200, > + .prim_fifo_threshold = 0x00010000, > + .bcms = (const struct a6xx_bcm[]) { > + { .name = "SH0", .buswidth = 16 }, > + { .name = "MC0", .buswidth = 4 }, > + { > + .name = "ACV", > + .fixed = true, > + .perfmode = BIT(3), > + }, > + { /* sentinel */ }, > + }, > + }, > + .address_space_size = SZ_16G, > }, { > .chip_ids = ADRENO_CHIP_IDS( > 0x06030001, > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 0ae29a7c8a4d..1820c167fcee 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -616,6 +616,14 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) > gpu->ubwc_config.uavflagprd_inv = 2; > } > > + if (adreno_is_a623(gpu)) { > + gpu->ubwc_config.highest_bank_bit = 16; > + gpu->ubwc_config.amsbc = 1; This bit causes my question: the patch for msm_mdss states that on the display side both UBWC encoder and decoder are 4.0, which means that the UBWC_AMSBC bit won't be set in the UBWC_STATIC register. > + gpu->ubwc_config.rgb565_predicator = 1; > + gpu->ubwc_config.uavflagprd_inv = 2; > + gpu->ubwc_config.macrotile_mode = 1; > + } > + > if (adreno_is_a640_family(gpu)) > gpu->ubwc_config.amsbc = 1; > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c > index 2c10474ccc95..3222a406d089 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c > @@ -1227,7 +1227,7 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu, > _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1], > &a6xx_state->gmu_registers[1], true); > > - if (adreno_is_a621(adreno_gpu)) > + if (adreno_is_a621(adreno_gpu) || adreno_is_a623(adreno_gpu)) > _a6xx_get_gmu_registers(gpu, a6xx_state, &a621_gpucc_reg, > &a6xx_state->gmu_registers[2], false); > else > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index dcf454629ce0..92caba3584da 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -442,6 +442,11 @@ static inline int adreno_is_a621(const struct adreno_gpu *gpu) > return gpu->info->chip_ids[0] == 0x06020100; > } > > +static inline int adreno_is_a623(const struct adreno_gpu *gpu) > +{ > + return gpu->info->chip_ids[0] == 0x06020300; > +} > + > static inline int adreno_is_a630(const struct adreno_gpu *gpu) > { > return adreno_is_revn(gpu, 630); > > -- > 2.45.2 >
On 13.02.2025 5:10 PM, Akhil P Oommen wrote: > From: Jie Zhang <quic_jiezh@quicinc.com> > > Add support for Adreno 623 GPU found in QCS8300 chipsets. > > Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +++++++++++++++++++++++++++++ > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ > drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > 4 files changed, 43 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index edffb7737a97..ac156c8b5af9 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -879,6 +879,35 @@ static const struct adreno_info a6xx_gpus[] = { > { 0, 0 }, > { 137, 1 }, > ), > + }, { > + .chip_ids = ADRENO_CHIP_IDS(0x06020300), > + .family = ADRENO_6XX_GEN3, > + .fw = { > + [ADRENO_FW_SQE] = "a650_sqe.fw", > + [ADRENO_FW_GMU] = "a623_gmu.bin", > + }, > + .gmem = SZ_512K, > + .inactive_period = DRM_MSM_INACTIVE_PERIOD, > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | > + ADRENO_QUIRK_HAS_HW_APRIV, > + .init = a6xx_gpu_init, > + .a6xx = &(const struct a6xx_info) { > + .hwcg = a620_hwcg, On downstream a663 hwcg table is used, with the following differences: < A620 > A663 < {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, > {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, < {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777}, > {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000} Konrad
On 2/13/2025 10:24 PM, Dmitry Baryshkov wrote: > On Thu, Feb 13, 2025 at 09:40:07PM +0530, Akhil P Oommen wrote: >> From: Jie Zhang <quic_jiezh@quicinc.com> >> >> Add support for Adreno 623 GPU found in QCS8300 chipsets. >> >> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> >> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >> --- >> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +++++++++++++++++++++++++++++ >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ >> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ >> 4 files changed, 43 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> index edffb7737a97..ac156c8b5af9 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> @@ -879,6 +879,35 @@ static const struct adreno_info a6xx_gpus[] = { >> { 0, 0 }, >> { 137, 1 }, >> ), >> + }, { >> + .chip_ids = ADRENO_CHIP_IDS(0x06020300), >> + .family = ADRENO_6XX_GEN3, >> + .fw = { >> + [ADRENO_FW_SQE] = "a650_sqe.fw", >> + [ADRENO_FW_GMU] = "a623_gmu.bin", >> + }, >> + .gmem = SZ_512K, >> + .inactive_period = DRM_MSM_INACTIVE_PERIOD, >> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | >> + ADRENO_QUIRK_HAS_HW_APRIV, >> + .init = a6xx_gpu_init, >> + .a6xx = &(const struct a6xx_info) { >> + .hwcg = a620_hwcg, >> + .protect = &a650_protect, >> + .gmu_cgc_mode = 0x00020200, >> + .prim_fifo_threshold = 0x00010000, >> + .bcms = (const struct a6xx_bcm[]) { >> + { .name = "SH0", .buswidth = 16 }, >> + { .name = "MC0", .buswidth = 4 }, >> + { >> + .name = "ACV", >> + .fixed = true, >> + .perfmode = BIT(3), >> + }, >> + { /* sentinel */ }, >> + }, >> + }, >> + .address_space_size = SZ_16G, >> }, { >> .chip_ids = ADRENO_CHIP_IDS( >> 0x06030001, >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index 0ae29a7c8a4d..1820c167fcee 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -616,6 +616,14 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) >> gpu->ubwc_config.uavflagprd_inv = 2; >> } >> >> + if (adreno_is_a623(gpu)) { >> + gpu->ubwc_config.highest_bank_bit = 16; >> + gpu->ubwc_config.amsbc = 1; > > This bit causes my question: the patch for msm_mdss states that on the > display side both UBWC encoder and decoder are 4.0, which means that the > UBWC_AMSBC bit won't be set in the UBWC_STATIC register. Not sure, but my guess is that AMSBC encoding is probably implicitly enabled by MDSS HW when UBWC v4 is configured. -Akhil > >> + gpu->ubwc_config.rgb565_predicator = 1; >> + gpu->ubwc_config.uavflagprd_inv = 2; >> + gpu->ubwc_config.macrotile_mode = 1; >> + } >> + >> if (adreno_is_a640_family(gpu)) >> gpu->ubwc_config.amsbc = 1; >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c >> index 2c10474ccc95..3222a406d089 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c >> @@ -1227,7 +1227,7 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu, >> _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1], >> &a6xx_state->gmu_registers[1], true); >> >> - if (adreno_is_a621(adreno_gpu)) >> + if (adreno_is_a621(adreno_gpu) || adreno_is_a623(adreno_gpu)) >> _a6xx_get_gmu_registers(gpu, a6xx_state, &a621_gpucc_reg, >> &a6xx_state->gmu_registers[2], false); >> else >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> index dcf454629ce0..92caba3584da 100644 >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> @@ -442,6 +442,11 @@ static inline int adreno_is_a621(const struct adreno_gpu *gpu) >> return gpu->info->chip_ids[0] == 0x06020100; >> } >> >> +static inline int adreno_is_a623(const struct adreno_gpu *gpu) >> +{ >> + return gpu->info->chip_ids[0] == 0x06020300; >> +} >> + >> static inline int adreno_is_a630(const struct adreno_gpu *gpu) >> { >> return adreno_is_revn(gpu, 630); >> >> -- >> 2.45.2 >> >
On Sat, 15 Feb 2025 at 13:49, Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: > > On 2/13/2025 10:24 PM, Dmitry Baryshkov wrote: > > On Thu, Feb 13, 2025 at 09:40:07PM +0530, Akhil P Oommen wrote: > >> From: Jie Zhang <quic_jiezh@quicinc.com> > >> > >> Add support for Adreno 623 GPU found in QCS8300 chipsets. > >> > >> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> > >> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > >> --- > >> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +++++++++++++++++++++++++++++ > >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ > >> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- > >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > >> 4 files changed, 43 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > >> index edffb7737a97..ac156c8b5af9 100644 > >> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > >> @@ -879,6 +879,35 @@ static const struct adreno_info a6xx_gpus[] = { > >> { 0, 0 }, > >> { 137, 1 }, > >> ), > >> + }, { > >> + .chip_ids = ADRENO_CHIP_IDS(0x06020300), > >> + .family = ADRENO_6XX_GEN3, > >> + .fw = { > >> + [ADRENO_FW_SQE] = "a650_sqe.fw", > >> + [ADRENO_FW_GMU] = "a623_gmu.bin", > >> + }, > >> + .gmem = SZ_512K, > >> + .inactive_period = DRM_MSM_INACTIVE_PERIOD, > >> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | > >> + ADRENO_QUIRK_HAS_HW_APRIV, > >> + .init = a6xx_gpu_init, > >> + .a6xx = &(const struct a6xx_info) { > >> + .hwcg = a620_hwcg, > >> + .protect = &a650_protect, > >> + .gmu_cgc_mode = 0x00020200, > >> + .prim_fifo_threshold = 0x00010000, > >> + .bcms = (const struct a6xx_bcm[]) { > >> + { .name = "SH0", .buswidth = 16 }, > >> + { .name = "MC0", .buswidth = 4 }, > >> + { > >> + .name = "ACV", > >> + .fixed = true, > >> + .perfmode = BIT(3), > >> + }, > >> + { /* sentinel */ }, > >> + }, > >> + }, > >> + .address_space_size = SZ_16G, > >> }, { > >> .chip_ids = ADRENO_CHIP_IDS( > >> 0x06030001, > >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > >> index 0ae29a7c8a4d..1820c167fcee 100644 > >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > >> @@ -616,6 +616,14 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) > >> gpu->ubwc_config.uavflagprd_inv = 2; > >> } > >> > >> + if (adreno_is_a623(gpu)) { > >> + gpu->ubwc_config.highest_bank_bit = 16; > >> + gpu->ubwc_config.amsbc = 1; > > > > This bit causes my question: the patch for msm_mdss states that on the > > display side both UBWC encoder and decoder are 4.0, which means that the > > UBWC_AMSBC bit won't be set in the UBWC_STATIC register. > > Not sure, but my guess is that AMSBC encoding is probably implicitly > enabled by MDSS HW when UBWC v4 is configured. Ack. > > -Akhil > > > > >> + gpu->ubwc_config.rgb565_predicator = 1; > >> + gpu->ubwc_config.uavflagprd_inv = 2; > >> + gpu->ubwc_config.macrotile_mode = 1; > >> + } > >> + > >> if (adreno_is_a640_family(gpu)) > >> gpu->ubwc_config.amsbc = 1; > >> > >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c > >> index 2c10474ccc95..3222a406d089 100644 > >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c > >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c > >> @@ -1227,7 +1227,7 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu, > >> _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1], > >> &a6xx_state->gmu_registers[1], true); > >> > >> - if (adreno_is_a621(adreno_gpu)) > >> + if (adreno_is_a621(adreno_gpu) || adreno_is_a623(adreno_gpu)) > >> _a6xx_get_gmu_registers(gpu, a6xx_state, &a621_gpucc_reg, > >> &a6xx_state->gmu_registers[2], false); > >> else > >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > >> index dcf454629ce0..92caba3584da 100644 > >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > >> @@ -442,6 +442,11 @@ static inline int adreno_is_a621(const struct adreno_gpu *gpu) > >> return gpu->info->chip_ids[0] == 0x06020100; > >> } > >> > >> +static inline int adreno_is_a623(const struct adreno_gpu *gpu) > >> +{ > >> + return gpu->info->chip_ids[0] == 0x06020300; > >> +} > >> + > >> static inline int adreno_is_a630(const struct adreno_gpu *gpu) > >> { > >> return adreno_is_revn(gpu, 630); > >> > >> -- > >> 2.45.2 > >> > > >
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index edffb7737a97..ac156c8b5af9 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -879,6 +879,35 @@ static const struct adreno_info a6xx_gpus[] = { { 0, 0 }, { 137, 1 }, ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06020300), + .family = ADRENO_6XX_GEN3, + .fw = { + [ADRENO_FW_SQE] = "a650_sqe.fw", + [ADRENO_FW_GMU] = "a623_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .a6xx = &(const struct a6xx_info) { + .hwcg = a620_hwcg, + .protect = &a650_protect, + .gmu_cgc_mode = 0x00020200, + .prim_fifo_threshold = 0x00010000, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(3), + }, + { /* sentinel */ }, + }, + }, + .address_space_size = SZ_16G, }, { .chip_ids = ADRENO_CHIP_IDS( 0x06030001, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0ae29a7c8a4d..1820c167fcee 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -616,6 +616,14 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.uavflagprd_inv = 2; } + if (adreno_is_a623(gpu)) { + gpu->ubwc_config.highest_bank_bit = 16; + gpu->ubwc_config.amsbc = 1; + gpu->ubwc_config.rgb565_predicator = 1; + gpu->ubwc_config.uavflagprd_inv = 2; + gpu->ubwc_config.macrotile_mode = 1; + } + if (adreno_is_a640_family(gpu)) gpu->ubwc_config.amsbc = 1; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index 2c10474ccc95..3222a406d089 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -1227,7 +1227,7 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu, _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1], &a6xx_state->gmu_registers[1], true); - if (adreno_is_a621(adreno_gpu)) + if (adreno_is_a621(adreno_gpu) || adreno_is_a623(adreno_gpu)) _a6xx_get_gmu_registers(gpu, a6xx_state, &a621_gpucc_reg, &a6xx_state->gmu_registers[2], false); else diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index dcf454629ce0..92caba3584da 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -442,6 +442,11 @@ static inline int adreno_is_a621(const struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x06020100; } +static inline int adreno_is_a623(const struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x06020300; +} + static inline int adreno_is_a630(const struct adreno_gpu *gpu) { return adreno_is_revn(gpu, 630);