| Message ID | 20250221-sar2130p-pci-v2-1-cc87590ffbeb@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: qcom-ep: add support for using the EP on SAR2130P and SM8450 | expand |
On 21/02/2025 04:06, Dmitry Baryshkov wrote: > Some of Qualcomm platforms have an IOMMU unit between the PCIe IP and > DDR. Changethe schema in order to allow specifying the IOMMU. Missing space - "Change the" > > Fixes: 9d3d5e75f31c ("dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > index 1226ee5d08d1ae909b07b0d78014618c4c74e9a8..800accdf5947e7178ad80f0759cf53111be1a814 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > @@ -75,6 +75,9 @@ properties: > - const: doorbell > - const: dma > > + iommus: > + maxItems: 1 > + > reset-gpios: > description: GPIO used as PERST# input signal > maxItems: 1 > @@ -233,6 +236,20 @@ allOf: > minItems: 3 > maxItems: 3 > > + - if: > + properties: > + compatible: > + contains: > + const: qcom,sdx55-pcie-ep > + then: > + properties: > + iommus: > + false iommus: false > + > + else: > + required: > + - iommus You make it required but commit msg does not explain that. It actually is quite permissive: "allow specifying". This is ABI break so either drop required or rephrase commit msg explaining why this has to be required now. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 1226ee5d08d1ae909b07b0d78014618c4c74e9a8..800accdf5947e7178ad80f0759cf53111be1a814 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -75,6 +75,9 @@ properties: - const: doorbell - const: dma + iommus: + maxItems: 1 + reset-gpios: description: GPIO used as PERST# input signal maxItems: 1 @@ -233,6 +236,20 @@ allOf: minItems: 3 maxItems: 3 + - if: + properties: + compatible: + contains: + const: qcom,sdx55-pcie-ep + then: + properties: + iommus: + false + + else: + required: + - iommus + unevaluatedProperties: false examples:
Some of Qualcomm platforms have an IOMMU unit between the PCIe IP and DDR. Changethe schema in order to allow specifying the IOMMU. Fixes: 9d3d5e75f31c ("dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)