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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54816a55851sm287643e87.27.2025.02.21.07.52.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:52:09 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 17:52:03 +0200 Subject: [PATCH v3 5/8] dt-bindings: PCI: qcom-ep: add SAR2130P compatible Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250221-sar2130p-pci-v3-5-61a0fdfb75b4@linaro.org> References: <20250221-sar2130p-pci-v3-0-61a0fdfb75b4@linaro.org> In-Reply-To: <20250221-sar2130p-pci-v3-0-61a0fdfb75b4@linaro.org> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2475; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=2EB6HQ3Xg729UaJzi6eQwoGHABfEKMGzkAxaHZxQ0PY=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnuKEhIOyO9evi4YM+xJTK2NM4Yj/jKLQrJ9Snz KarRzpLmseJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ7ihIQAKCRAU23LtvoBl uIa5D/95JI992C4uMMAmvNAtQO1N1b1d3cIaBQQVRB+Z6u8P4D13JhJcv4BtFqF0hzhQolon93z 9l3Xt0lR2aSvVR/1BELh26VmhYUXIMJJlan2zlWPz5VQ+TucKB+9gdO3gsoJvGcDx/e7p5uhjkC dM89xqHhbhO3Yj7Yuv5wDiYg7RhcQebXG5nrkTRaRK4XJC1+vJhfd2CG0Jq3T2hRXDDUGZqzuXg 5B50dWo/fCPli8sPsFf9Zj/aRFqTZzbMRD3LDu2aSU/YRzKCoUJkwY2q5+IZjoKDyFXn0zsHuf3 7Ei7ogJ+tO4A46l1sGyUNJZrhWnR2jtH1Z1cWOf137KJbT8Y62gbK4hHJtXDlCU0FMN3ApMAIPs Xg980d93pVpCE2ttFBhB4ZkZ13DkG1p8QwE24r7ynV7nRUf9Z8Xy583X3xRiDy5wLHUJFrqydz2 iyob4YM5FqEN317+gQBddC7V5v+XYKfhDMmHk1oRB0rRE2bt1zRmBTVMQknOn762+l1XvfcQYps lKXUmK5gvMjE/QW9Ck+fVLaL6zjaUuk+xxcK2fJpzmkWmBXylrojfbv2clYbpQv+IGDU7xS4S1b pbqm+OUBd+A7zktC5r1T52ZtIEYLmwQrlPQAMjO9H8g1vJ6D1Z48OB4qFpbV6mtuR95cCGJO41X okUVDAdDo5Pgung== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Add support for using the PCI controller in the endpoint mode on the SAR2130P platform. It is impossible to use fallback compatible to any other platform since SAR2130P uses slightly different set of clocks. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 36 ++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 2c1918ca30dcfa8decea684ff6bfe11c602bbc7e..ac3414203d383bbd1a520dc11f317a5da9ca33e4 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - qcom,sa8775p-pcie-ep + - qcom,sar2130p-pcie-ep - qcom,sdx55-pcie-ep - qcom,sm8450-pcie-ep - items: @@ -44,11 +45,11 @@ properties: clocks: minItems: 5 - maxItems: 8 + maxItems: 9 clock-names: minItems: 5 - maxItems: 8 + maxItems: 9 qcom,perst-regs: description: Reference to a syscon representing TCSR followed by the two @@ -132,6 +133,37 @@ required: allOf: - $ref: pci-ep.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sar2130p-pcie-ep + then: + properties: + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe DDRSS SF TBU clock + - description: PCIe AGGRE NOC AXI clock + - description: PCIe CFG NOC AXI clock + - description: PCIe QMIP AHB clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: ddrss_sf_tbu + - const: aggre_noc_axi + - const: cnoc_sf_axi + - const: qmip_pcie_ahb + - if: properties: compatible: