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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Only CPU0 Embedded Trace Extension (ETE) was added, but there's one for all 8 CPUs, so add the missing ones. Fixes: 256e6937e48a ("arm64: dts: qcom: sm8650: Add coresight nodes") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong --- Changes in v3: - rebased on linux-next - Link to v2: https://lore.kernel.org/r/20250129-topic-sm8650-upstream-add-all-coresight-cpus-v2-1-c62549307e01@linaro.org Changes in v2: - fixed the 7/8 cpu wording - added the sm8650 prefix - add review tag - Link to v1: https://lore.kernel.org/r/20250129-topic-sm8650-upstream-add-all-coresight-cpus-v1-1-96996d37df8e@linaro.org --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 163 ++++++++++++++++++++++++++++++++++- 1 file changed, 161 insertions(+), 2 deletions(-) --- base-commit: be5c7bbb3a64baf884481a1ba0c2f8fb2f93f7c3 change-id: 20250129-topic-sm8650-upstream-add-all-coresight-cpus-a3418606b354 Best regards, diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 09cc884f0969432c53671e804ec6a3f7643fc0a9..c5fe5b88183f19d5dd9aef7f898e0badc192011f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -438,7 +438,7 @@ cluster_sleep_1: cluster-sleep-1 { }; }; - ete0 { + ete-0 { compatible = "arm,embedded-trace-extension"; cpu = <&cpu0>; @@ -452,15 +452,174 @@ ete0_out_funnel_ete: endpoint { }; }; + ete-1 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu1>; + + out-ports { + port { + ete1_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete1>; + }; + }; + }; + }; + + ete-2 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu2>; + + out-ports { + port { + ete2_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete2>; + }; + }; + }; + }; + + ete-3 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu3>; + + out-ports { + port { + ete3_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete3>; + }; + }; + }; + }; + + ete-4 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu4>; + + out-ports { + port { + ete4_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete4>; + }; + }; + }; + }; + + ete-5 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu5>; + + out-ports { + port { + ete5_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete5>; + }; + }; + }; + }; + + ete-6 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu6>; + + out-ports { + port { + ete6_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete6>; + }; + }; + }; + }; + + ete-7 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu7>; + + out-ports { + port { + ete7_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete7>; + }; + }; + }; + }; + funnel-ete { compatible = "arm,coresight-static-funnel"; in-ports { - port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ete_in_ete0: endpoint { remote-endpoint = <&ete0_out_funnel_ete>; }; }; + + port@1 { + reg = <1>; + + funnel_ete_in_ete1: endpoint { + remote-endpoint = <&ete1_out_funnel_ete>; + }; + }; + + port@2 { + reg = <2>; + + funnel_ete_in_ete2: endpoint { + remote-endpoint = <&ete2_out_funnel_ete>; + }; + }; + + port@3 { + reg = <3>; + + funnel_ete_in_ete3: endpoint { + remote-endpoint = <&ete3_out_funnel_ete>; + }; + }; + + port@4 { + reg = <4>; + + funnel_ete_in_ete4: endpoint { + remote-endpoint = <&ete4_out_funnel_ete>; + }; + }; + + port@5 { + reg = <5>; + + funnel_ete_in_ete5: endpoint { + remote-endpoint = <&ete5_out_funnel_ete>; + }; + }; + + port@6 { + reg = <6>; + + funnel_ete_in_ete6: endpoint { + remote-endpoint = <&ete6_out_funnel_ete>; + }; + }; + + port@7 { + reg = <7>; + + funnel_ete_in_ete7: endpoint { + remote-endpoint = <&ete7_out_funnel_ete>; + }; + }; }; out-ports {