| Message ID | 20250306-videocc-pll-multi-pd-voting-v2-2-0cd00612bc0e@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | clk: qcom: Add support to attach multiple power domains in cc probe | expand |
On 6.03.2025 9:55 AM, Jagadeesh Kona wrote: > From: Taniya Das <quic_tdas@quicinc.com> > > Integrate PLL configuration into clk_alpha_pll structure and add support > for qcom_cc_clk_alpha_pll_configure() function which can be used to > configure the clock controller PLLs from common core code. > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > --- [...] > +static void qcom_cc_clk_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap) > +{ > + if (!pll->config || !pll->regs) > + return; This should probably throw some sort of a warning > + > + switch (GET_PLL_TYPE(pll)) { > + case CLK_ALPHA_PLL_TYPE_LUCID_OLE: > + clk_lucid_ole_pll_configure(pll, regmap, pll->config); > + break; > + case CLK_ALPHA_PLL_TYPE_LUCID_EVO: > + clk_lucid_evo_pll_configure(pll, regmap, pll->config); > + break; > + case CLK_ALPHA_PLL_TYPE_TAYCAN_ELU: > + clk_taycan_elu_pll_configure(pll, regmap, pll->config); > + break; > + case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO: > + clk_rivian_evo_pll_configure(pll, regmap, pll->config); > + break; > + case CLK_ALPHA_PLL_TYPE_TRION: > + clk_trion_pll_configure(pll, regmap, pll->config); > + break; > + case CLK_ALPHA_PLL_TYPE_HUAYRA_2290: > + clk_huayra_2290_pll_configure(pll, regmap, pll->config); > + break; > + case CLK_ALPHA_PLL_TYPE_FABIA: > + clk_fabia_pll_configure(pll, regmap, pll->config); > + break; > + case CLK_ALPHA_PLL_TYPE_AGERA: > + clk_agera_pll_configure(pll, regmap, pll->config); > + break; > + case CLK_ALPHA_PLL_TYPE_PONGO_ELU: > + clk_pongo_elu_pll_configure(pll, regmap, pll->config); > + break; > + case CLK_ALPHA_PLL_TYPE_ZONDA: > + case CLK_ALPHA_PLL_TYPE_ZONDA_OLE: > + clk_zonda_pll_configure(pll, regmap, pll->config); > + break; > + case CLK_ALPHA_PLL_TYPE_STROMER: > + case CLK_ALPHA_PLL_TYPE_STROMER_PLUS: > + clk_stromer_pll_configure(pll, regmap, pll->config); > + break; > + case CLK_ALPHA_PLL_TYPE_DEFAULT: > + case CLK_ALPHA_PLL_TYPE_DEFAULT_EVO: > + case CLK_ALPHA_PLL_TYPE_HUAYRA: > + case CLK_ALPHA_PLL_TYPE_HUAYRA_APSS: > + case CLK_ALPHA_PLL_TYPE_BRAMMO: > + case CLK_ALPHA_PLL_TYPE_BRAMMO_EVO: > + clk_alpha_pll_configure(pll, regmap, pll->config); > + break; > + default: > + break; And so should the 'default' case Konrad
On 3/6/2025 5:52 PM, Konrad Dybcio wrote: > On 6.03.2025 9:55 AM, Jagadeesh Kona wrote: >> From: Taniya Das <quic_tdas@quicinc.com> >> >> Integrate PLL configuration into clk_alpha_pll structure and add support >> for qcom_cc_clk_alpha_pll_configure() function which can be used to >> configure the clock controller PLLs from common core code. >> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> --- > > [...] > >> +static void qcom_cc_clk_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap) >> +{ >> + if (!pll->config || !pll->regs) >> + return; > > This should probably throw some sort of a warning > Yes, will add a warning here and for default case in next series. Thanks, Jagadeesh >> + >> + switch (GET_PLL_TYPE(pll)) { >> + case CLK_ALPHA_PLL_TYPE_LUCID_OLE: >> + clk_lucid_ole_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_LUCID_EVO: >> + clk_lucid_evo_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_TAYCAN_ELU: >> + clk_taycan_elu_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO: >> + clk_rivian_evo_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_TRION: >> + clk_trion_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_HUAYRA_2290: >> + clk_huayra_2290_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_FABIA: >> + clk_fabia_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_AGERA: >> + clk_agera_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_PONGO_ELU: >> + clk_pongo_elu_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_ZONDA: >> + case CLK_ALPHA_PLL_TYPE_ZONDA_OLE: >> + clk_zonda_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_STROMER: >> + case CLK_ALPHA_PLL_TYPE_STROMER_PLUS: >> + clk_stromer_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_DEFAULT: >> + case CLK_ALPHA_PLL_TYPE_DEFAULT_EVO: >> + case CLK_ALPHA_PLL_TYPE_HUAYRA: >> + case CLK_ALPHA_PLL_TYPE_HUAYRA_APSS: >> + case CLK_ALPHA_PLL_TYPE_BRAMMO: >> + case CLK_ALPHA_PLL_TYPE_BRAMMO_EVO: >> + clk_alpha_pll_configure(pll, regmap, pll->config); >> + break; >> + default: >> + break; > > And so should the 'default' case > > Konrad
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 79aca8525262211ae5295245427d4540abf1e09a..943320cdcd10a6c07fcd74dccb88be847dc086c2 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -81,6 +81,7 @@ struct pll_vco { * struct clk_alpha_pll - phase locked loop (PLL) * @offset: base address of registers * @regs: alpha pll register map (see @clk_alpha_pll_regs) + * @config: array of pll settings * @vco_table: array of VCO settings * @num_vco: number of VCO settings in @vco_table * @flags: bitmask to indicate features supported by the hardware @@ -90,6 +91,7 @@ struct clk_alpha_pll { u32 offset; const u8 *regs; + const struct alpha_pll_config *config; const struct pll_vco *vco_table; size_t num_vco; #define SUPPORTS_OFFLINE_REQ BIT(0) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 9e3380fd718198c9fe63d7361615a91c3ecb3d60..74d062b5da0647f7f2bd8fd7a004ffdb1116c1ea 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -13,6 +13,7 @@ #include <linux/of.h> #include "common.h" +#include "clk-alpha-pll.h" #include "clk-rcg.h" #include "clk-regmap.h" #include "reset.h" @@ -284,6 +285,60 @@ static int qcom_cc_icc_register(struct device *dev, desc->num_icc_hws, icd); } +static void qcom_cc_clk_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap) +{ + if (!pll->config || !pll->regs) + return; + + switch (GET_PLL_TYPE(pll)) { + case CLK_ALPHA_PLL_TYPE_LUCID_OLE: + clk_lucid_ole_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_LUCID_EVO: + clk_lucid_evo_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_TAYCAN_ELU: + clk_taycan_elu_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO: + clk_rivian_evo_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_TRION: + clk_trion_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_HUAYRA_2290: + clk_huayra_2290_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_FABIA: + clk_fabia_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_AGERA: + clk_agera_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_PONGO_ELU: + clk_pongo_elu_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_ZONDA: + case CLK_ALPHA_PLL_TYPE_ZONDA_OLE: + clk_zonda_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_STROMER: + case CLK_ALPHA_PLL_TYPE_STROMER_PLUS: + clk_stromer_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_DEFAULT: + case CLK_ALPHA_PLL_TYPE_DEFAULT_EVO: + case CLK_ALPHA_PLL_TYPE_HUAYRA: + case CLK_ALPHA_PLL_TYPE_HUAYRA_APSS: + case CLK_ALPHA_PLL_TYPE_BRAMMO: + case CLK_ALPHA_PLL_TYPE_BRAMMO_EVO: + clk_alpha_pll_configure(pll, regmap, pll->config); + break; + default: + break; + } +} + int qcom_cc_really_probe(struct device *dev, const struct qcom_cc_desc *desc, struct regmap *regmap) { diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index 7ace5d7f5836aa81431153ba92d8f14f2ffe8147..2066c8937936235d7bd03ab3225d4b3f4fb08dd0 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -18,6 +18,7 @@ struct clk_hw; #define PLL_BIAS_COUNT_MASK 0x3f #define PLL_VOTE_FSM_ENA BIT(20) #define PLL_VOTE_FSM_RESET BIT(21) +#define GET_PLL_TYPE(pll) ((pll->regs - clk_alpha_pll_regs[0]) / PLL_OFF_MAX_REGS) struct qcom_icc_hws_data { int master_id;