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Thu, 6 Mar 2025 08:56:06 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Mar 2025 00:56:02 -0800 From: Jagadeesh Kona Date: Thu, 6 Mar 2025 14:25:35 +0530 Subject: [PATCH v2 3/8] clk: qcom: common: Manage rpm, configure PLLs & AON clks in really probe Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250306-videocc-pll-multi-pd-voting-v2-3-0cd00612bc0e@quicinc.com> References: <20250306-videocc-pll-multi-pd-voting-v2-0-0cd00612bc0e@quicinc.com> In-Reply-To: <20250306-videocc-pll-multi-pd-voting-v2-0-0cd00612bc0e@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Jagadeesh Kona X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Jxf1SCCsxuJC9l1M7bnrxGYXlGvOUjE7 X-Authority-Analysis: v=2.4 cv=cOIaskeN c=1 sm=1 tr=0 ts=67c96327 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=yLKRu0m9bsFlKXT4E7YA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: Jxf1SCCsxuJC9l1M7bnrxGYXlGvOUjE7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-06_04,2025-03-06_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 adultscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503060067 Add support for runtime power management, PLL configuration and enabling critical clocks in qcom_cc_really_probe() to commonize the clock controller probe. The runtime power management is not required for all clock controllers, hence handle the rpm based on use_rpm flag in clock controller descriptor. Also the power domains need to be kept enabled during pll configuration, hence attach all required power domains prior to calling get_sync() on the device. Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/common.c | 45 ++++++++++++++++++++++++++++++++++++--------- drivers/clk/qcom/common.h | 16 ++++++++++++++++ 2 files changed, 52 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 74d062b5da0647f7f2bd8fd7a004ffdb1116c1ea..ce87f74fa51639ed270a0c56fff1cd2845885647 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -350,6 +351,7 @@ int qcom_cc_really_probe(struct device *dev, struct clk_regmap **rclks = desc->clks; size_t num_clk_hws = desc->num_clk_hws; struct clk_hw **clk_hws = desc->clk_hws; + struct qcom_clk_cfg *clks_cfg = desc->clks_cfg; cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL); if (!cc) @@ -359,6 +361,23 @@ int qcom_cc_really_probe(struct device *dev, if (ret < 0 && ret != -EEXIST) return ret; + if (desc->use_rpm) { + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + } + + for (i = 0; i < desc->num_plls; i++) + qcom_cc_clk_pll_configure(desc->plls[i], regmap); + + for (i = 0 ; i < desc->num_clks_cfg; i++) + regmap_update_bits(regmap, clks_cfg[i].offset, + clks_cfg[i].mask, clks_cfg[i].mask); + reset = &cc->reset; reset->rcdev.of_node = dev->of_node; reset->rcdev.ops = &qcom_reset_ops; @@ -369,23 +388,25 @@ int qcom_cc_really_probe(struct device *dev, ret = devm_reset_controller_register(dev, &reset->rcdev); if (ret) - return ret; + goto put_rpm; if (desc->gdscs && desc->num_gdscs) { scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL); - if (!scd) - return -ENOMEM; + if (!scd) { + ret = -ENOMEM; + goto put_rpm; + } scd->dev = dev; scd->scs = desc->gdscs; scd->num = desc->num_gdscs; scd->pd_list = cc->pd_list; ret = gdsc_register(scd, &reset->rcdev, regmap); if (ret) - return ret; + goto put_rpm; ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister, scd); if (ret) - return ret; + goto put_rpm; } cc->rclks = rclks; @@ -396,7 +417,7 @@ int qcom_cc_really_probe(struct device *dev, for (i = 0; i < num_clk_hws; i++) { ret = devm_clk_hw_register(dev, clk_hws[i]); if (ret) - return ret; + goto put_rpm; } for (i = 0; i < num_clks; i++) { @@ -405,14 +426,20 @@ int qcom_cc_really_probe(struct device *dev, ret = devm_clk_register_regmap(dev, rclks[i]); if (ret) - return ret; + goto put_rpm; } ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc); if (ret) - return ret; + goto put_rpm; + + ret = qcom_cc_icc_register(dev, desc); + +put_rpm: + if (desc->use_rpm) + pm_runtime_put(dev); - return qcom_cc_icc_register(dev, desc); + return ret; } EXPORT_SYMBOL_GPL(qcom_cc_really_probe); diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index 2066c8937936235d7bd03ab3225d4b3f4fb08dd0..da27290b7da3ddc6d8ba1b064619e294bfcb686c 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -26,6 +26,17 @@ struct qcom_icc_hws_data { int clk_id; }; +/** + * struct qcom_clk_cfg - To maintain list of clocks that needs to be + * kept ON or misc clock register settings + * @offset: address offset for clock register + * @mask: bit mask to indicate the bits to update + */ +struct qcom_clk_cfg { + unsigned int offset; + unsigned int mask; +}; + struct qcom_cc_desc { const struct regmap_config *config; struct clk_regmap **clks; @@ -39,6 +50,11 @@ struct qcom_cc_desc { const struct qcom_icc_hws_data *icc_hws; size_t num_icc_hws; unsigned int icc_first_node_id; + struct qcom_clk_cfg *clks_cfg; + size_t num_clks_cfg; + struct clk_alpha_pll **plls; + size_t num_plls; + bool use_rpm; }; /**