diff mbox series

[v1] arm64: dts: qcom: ipq9574: fix the msi interrupt numbers of pcie3

Message ID 20250313071422.510-1-quic_mmanikan@quicinc.com (mailing list archive)
State Accepted
Headers show
Series [v1] arm64: dts: qcom: ipq9574: fix the msi interrupt numbers of pcie3 | expand

Commit Message

Manikanta Mylavarapu March 13, 2025, 7:14 a.m. UTC
The MSI interrupt numbers of the PCIe3 controller are incorrect. Due
to this, the functional bring up of the QDSP6 processor on the PCIe
endpoint has failed. Correct the MSI interrupt numbers to properly
bring up the QDSP6 processor on the PCIe endpoint.

Fixes: d80c7fbfa908 ("arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes")
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)


base-commit: eea255893718268e1ab852fb52f70c613d109b99

Comments

Bjorn Andersson March 14, 2025, 8:01 p.m. UTC | #1
On Thu, 13 Mar 2025 12:44:22 +0530, Manikanta Mylavarapu wrote:
> The MSI interrupt numbers of the PCIe3 controller are incorrect. Due
> to this, the functional bring up of the QDSP6 processor on the PCIe
> endpoint has failed. Correct the MSI interrupt numbers to properly
> bring up the QDSP6 processor on the PCIe endpoint.
> 
> 

Applied, thanks!

[1/1] arm64: dts: qcom: ipq9574: fix the msi interrupt numbers of pcie3
      commit: c87d58bc7f831bf3d887e6ec846246cb673c2e50

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index cac58352182e..692c52a87bd1 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -972,14 +972,14 @@  pcie3: pcie@18000000 {
 			ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>,
 				 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>;
 
-			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi0",
 					  "msi1",
 					  "msi2",