| Message ID | 20250318093350.2682132-2-quic_stonez@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable WLAN for qcs8300-ride | expand |
On 3/18/25 10:33 AM, Stone Zhang wrote: > Add an original PCIe port for WLAN. This port will be > referenced and supplemented by specific WLAN devices. > > Signed-off-by: Stone Zhang <quic_stonez@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > index 8c141f0b414c..e25223d5be5e 100644 > --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > @@ -2091,6 +2091,15 @@ opp-32000000 { > opp-peak-kBps = <3938000 1>; > }; > }; > + > + pcieport0: pcie@0 { Because there's two PCIe hosts on this platform, please rename this global symbol to pcie0_port0. Konrad
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 8c141f0b414c..e25223d5be5e 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -2091,6 +2091,15 @@ opp-32000000 { opp-peak-kBps = <3938000 1>; }; }; + + pcieport0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + bus-range = <0x01 0xff>; + }; }; pcie0_phy: phy@1c04000 {
Add an original PCIe port for WLAN. This port will be referenced and supplemented by specific WLAN devices. Signed-off-by: Stone Zhang <quic_stonez@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)