From patchwork Fri Mar 21 12:14:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem X-Patchwork-Id: 14025343 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA0C622836C; Fri, 21 Mar 2025 12:14:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742559287; cv=none; b=JT50scpeh39EzJxCY8nf6ZjEtZg7GzDTZcM252aaczgeHdr3dNiifzb1v+dzheYnq+EOyIPMUGiru/a/ECFdstwLMrhAeDCovlkjcvEB+FKhT54Bp6WfCzKbZzTQmOLNd0tNCnqXdRBcJvRwB1JJbovyP7V7JvQMBMaDaAMhIIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742559287; c=relaxed/simple; bh=nnuDNLDyUo2HnSwQbCKlDNn2ZEgXZ5vT6V3g5jpmKio=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ahMYmt345E4Ogzfah71osBSnZIgUcoV0OCZHnIE2ejK3s6ytVAOqfCE4AucAq/EW89eM37PpsgdGkl5eQ+LtogjBL20Gf7refVoRuhsUWxARvl+krX9KTOsmt31b/3GDjkqUDarSTFO4wk76ttk2YRotqJm3mCjgkoE3KZ5lmB4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VNoThOAP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VNoThOAP" Received: by smtp.kernel.org (Postfix) with ESMTPS id 53D02C116B1; Fri, 21 Mar 2025 12:14:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742559286; bh=nnuDNLDyUo2HnSwQbCKlDNn2ZEgXZ5vT6V3g5jpmKio=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=VNoThOAPpjQ9G0y+s28YJoBGWyRhzLu1azJO6CZvoGkAWV1d6xxFhIXS+Uqj9vucG e22plLjbeNRJIYP7Pmlikn3uMqkAbyJoRh7HQqd976YpHKUV/g8lVFVpwNfIV/Qkae B/yPgIFmzj2uANWvQ1vPTBFeUHSMUcC3GTMZObCMQoo+tA1eY9D0ghPdaJzy2p8+lX Hp26/oFcAhm153lirile5bCA3QbhRJcmxzoQ785XKQssn39uCSMdW/EGiHXiCSsRjg xgq4XbicpK5IJrViIwt+5odTUT0fxlDoCQT6pBFN9/7hh07M2ZF6bioSIjgnzLGl7v iywZBPDm2lKXw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 498E0C36002; Fri, 21 Mar 2025 12:14:46 +0000 (UTC) Date: Fri, 21 Mar 2025 16:14:44 +0400 Subject: [PATCH v6 6/6] arm64: dts: qcom: ipq5018: Enable PCIe Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250321-ipq5018-pcie-v6-6-b7d659a76205@outlook.com> References: <20250321-ipq5018-pcie-v6-0-b7d659a76205@outlook.com> In-Reply-To: <20250321-ipq5018-pcie-v6-0-b7d659a76205@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nitheesh Sekar , Varadarajan Narayanan , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, George Moussalem , 20250317100029.881286-2-quic_varada@quicinc.com, Sricharan Ramabadhran X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1742559282; l=1810; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=aDrKqvqd+UP39quMJDnTOhOkR2gW/8ZVcG8WbwkiLrs=; b=7lZBmKLFQ3KtAnmMAeaVHaUvVUTADHpHpYCQZq9xoWlfiwZ9QZ6e/eutzAlkEX03b4IF3U/LQ qzmQNOwBuyTB8dBU4ldiAoJ8nBgKVtdOXpCYCNDNNQTc1UJDS6qFGKB X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem From: Nitheesh Sekar Enable the PCIe controller and PHY nodes for RDP 432-c2. Signed-off-by: Nitheesh Sekar Signed-off-by: Sricharan Ramabadhran Signed-off-by: George Moussalem Reviewed-by: Dmitry Baryshkov Acked-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 40 ++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts index 8460b538eb6a..43def95e9275 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -9,6 +9,8 @@ #include "ipq5018.dtsi" +#include + / { model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2"; compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018"; @@ -28,6 +30,20 @@ &blsp1_uart1 { status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; +}; + &sdhc_1 { pinctrl-0 = <&sdc_default_state>; pinctrl-names = "default"; @@ -43,6 +59,30 @@ &sleep_clk { }; &tlmm { + pcie0_default: pcie0-default-state { + clkreq-n-pins { + pins = "gpio14"; + function = "pcie0_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio15"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio16"; + function = "pcie0_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio9";