diff mbox series

arm64: dts: qcom: qcm2290: Add crypto engine

Message ID 20250327142842.1138203-1-loic.poulain@oss.qualcomm.com (mailing list archive)
State Superseded
Headers show
Series arm64: dts: qcom: qcm2290: Add crypto engine | expand

Commit Message

Loic Poulain March 27, 2025, 2:28 p.m. UTC 
Add Qualcomm Crypto Engine (QCE) and BAM related nodes for this SoC.

Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/qcm2290.dtsi | 28 +++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

Comments

Dmitry Baryshkov March 27, 2025, 3:05 p.m. UTC | #1 
On Thu, Mar 27, 2025 at 03:28:42PM +0100, Loic Poulain wrote:
> Add Qualcomm Crypto Engine (QCE) and BAM related nodes for this SoC.
> 
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/qcm2290.dtsi | 28 +++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> index f0746123e594..c9ac06164d43 100644
> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> @@ -749,6 +749,34 @@ config_noc: interconnect@1900000 {
>  			#interconnect-cells = <2>;
>  		};
>  
> +		cryptobam: dma@1b04000 {
> +			compatible = "qcom,bam-v1.7.0";
> +			reg = <0x0 0x01b04000 0x0 0x24000>;
> +			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
> +			clock-names = "bam_clk";
> +			#dma-cells = <1>;
> +			qcom,ee = <0>;
> +			qcom,controlled-remotely;
> +			iommus = <&apps_smmu 0x0084 0x0011>,
> +				 <&apps_smmu 0x0086 0x0011>,
> +				 <&apps_smmu 0x0094 0x0011>,
> +				 <&apps_smmu 0x0096 0x0011>;
> +		};
> +
> +		crypto: crypto@1b3a000 {
> +			compatible = "qcom,qcm2290-qce", "qcom,qce";
> +			reg = <0x0 0x01b3a000 0x0 0x6000>;
> +			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
> +			clock-names = "core";
> +			dmas = <&cryptobam 6>, <&cryptobam 7>;
> +			dma-names = "rx", "tx";
> +			iommus = <&apps_smmu 0x0084 0x0011>,
> +				 <&apps_smmu 0x0086 0x0011>,
> +				 <&apps_smmu 0x0094 0x0011>,
> +				 <&apps_smmu 0x0096 0x0011>;

Don't these fall into the previous entries + mask? The same question
applies to BAM SMMU entries.

> +		};
> +
>  		qfprom@1b44000 {
>  			compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
>  			reg = <0x0 0x01b44000 0x0 0x3000>;
> -- 
> 2.34.1
>
Konrad Dybcio March 27, 2025, 5:13 p.m. UTC | #2 
On 3/27/25 4:05 PM, Dmitry Baryshkov wrote:
> On Thu, Mar 27, 2025 at 03:28:42PM +0100, Loic Poulain wrote:
>> Add Qualcomm Crypto Engine (QCE) and BAM related nodes for this SoC.
>>
>> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
>> ---
>>  arch/arm64/boot/dts/qcom/qcm2290.dtsi | 28 +++++++++++++++++++++++++++
>>  1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>> index f0746123e594..c9ac06164d43 100644
>> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>> @@ -749,6 +749,34 @@ config_noc: interconnect@1900000 {
>>  			#interconnect-cells = <2>;
>>  		};
>>  
>> +		cryptobam: dma@1b04000 {
>> +			compatible = "qcom,bam-v1.7.0";
>> +			reg = <0x0 0x01b04000 0x0 0x24000>;
>> +			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
>> +			clock-names = "bam_clk";
>> +			#dma-cells = <1>;
>> +			qcom,ee = <0>;
>> +			qcom,controlled-remotely;
>> +			iommus = <&apps_smmu 0x0084 0x0011>,
>> +				 <&apps_smmu 0x0086 0x0011>,
>> +				 <&apps_smmu 0x0094 0x0011>,
>> +				 <&apps_smmu 0x0096 0x0011>;
>> +		};
>> +
>> +		crypto: crypto@1b3a000 {
>> +			compatible = "qcom,qcm2290-qce", "qcom,qce";
>> +			reg = <0x0 0x01b3a000 0x0 0x6000>;
>> +			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
>> +			clock-names = "core";
>> +			dmas = <&cryptobam 6>, <&cryptobam 7>;
>> +			dma-names = "rx", "tx";
>> +			iommus = <&apps_smmu 0x0084 0x0011>,
>> +				 <&apps_smmu 0x0086 0x0011>,
>> +				 <&apps_smmu 0x0094 0x0011>,
>> +				 <&apps_smmu 0x0096 0x0011>;
> 
> Don't these fall into the previous entries + mask? The same question
> applies to BAM SMMU entries.

(effective sid = e.g. 0x0084 & ~0x0011)

Konrad
Dmitry Baryshkov March 27, 2025, 6:17 p.m. UTC | #3 
On Thu, Mar 27, 2025 at 06:13:29PM +0100, Konrad Dybcio wrote:
> On 3/27/25 4:05 PM, Dmitry Baryshkov wrote:
> > On Thu, Mar 27, 2025 at 03:28:42PM +0100, Loic Poulain wrote:
> >> Add Qualcomm Crypto Engine (QCE) and BAM related nodes for this SoC.
> >>
> >> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> >> ---
> >>  arch/arm64/boot/dts/qcom/qcm2290.dtsi | 28 +++++++++++++++++++++++++++
> >>  1 file changed, 28 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> >> index f0746123e594..c9ac06164d43 100644
> >> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> >> @@ -749,6 +749,34 @@ config_noc: interconnect@1900000 {
> >>  			#interconnect-cells = <2>;
> >>  		};
> >>  
> >> +		cryptobam: dma@1b04000 {
> >> +			compatible = "qcom,bam-v1.7.0";
> >> +			reg = <0x0 0x01b04000 0x0 0x24000>;
> >> +			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
> >> +			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
> >> +			clock-names = "bam_clk";
> >> +			#dma-cells = <1>;
> >> +			qcom,ee = <0>;
> >> +			qcom,controlled-remotely;
> >> +			iommus = <&apps_smmu 0x0084 0x0011>,
> >> +				 <&apps_smmu 0x0086 0x0011>,
> >> +				 <&apps_smmu 0x0094 0x0011>,
> >> +				 <&apps_smmu 0x0096 0x0011>;
> >> +		};
> >> +
> >> +		crypto: crypto@1b3a000 {
> >> +			compatible = "qcom,qcm2290-qce", "qcom,qce";
> >> +			reg = <0x0 0x01b3a000 0x0 0x6000>;
> >> +			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
> >> +			clock-names = "core";
> >> +			dmas = <&cryptobam 6>, <&cryptobam 7>;
> >> +			dma-names = "rx", "tx";
> >> +			iommus = <&apps_smmu 0x0084 0x0011>,
> >> +				 <&apps_smmu 0x0086 0x0011>,
> >> +				 <&apps_smmu 0x0094 0x0011>,
> >> +				 <&apps_smmu 0x0096 0x0011>;
> > 
> > Don't these fall into the previous entries + mask? The same question
> > applies to BAM SMMU entries.
> 
> (effective sid = e.g. 0x0084 & ~0x0011)

Yes, 0x0094 & ~0x0011 = 0x0084.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
index f0746123e594..c9ac06164d43 100644
--- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
@@ -749,6 +749,34 @@  config_noc: interconnect@1900000 {
 			#interconnect-cells = <2>;
 		};
 
+		cryptobam: dma@1b04000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x0 0x01b04000 0x0 0x24000>;
+			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			qcom,controlled-remotely;
+			iommus = <&apps_smmu 0x0084 0x0011>,
+				 <&apps_smmu 0x0086 0x0011>,
+				 <&apps_smmu 0x0094 0x0011>,
+				 <&apps_smmu 0x0096 0x0011>;
+		};
+
+		crypto: crypto@1b3a000 {
+			compatible = "qcom,qcm2290-qce", "qcom,qce";
+			reg = <0x0 0x01b3a000 0x0 0x6000>;
+			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
+			clock-names = "core";
+			dmas = <&cryptobam 6>, <&cryptobam 7>;
+			dma-names = "rx", "tx";
+			iommus = <&apps_smmu 0x0084 0x0011>,
+				 <&apps_smmu 0x0086 0x0011>,
+				 <&apps_smmu 0x0094 0x0011>,
+				 <&apps_smmu 0x0096 0x0011>;
+		};
+
 		qfprom@1b44000 {
 			compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
 			reg = <0x0 0x01b44000 0x0 0x3000>;