| Message ID | 20250403102256.101217-2-loic.poulain@oss.qualcomm.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v3,1/2] dt-bindings: i2c: qcom-cci: Document QCM2290 compatible | expand |
On 03/04/2025 11:22, Loic Poulain wrote: > Add Camera Control Interface (CCI), supporting two I2C masters. > > Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> > --- > v2: Reorder commits; Update dts properties order and style > v3: No change for this patch > > arch/arm64/boot/dts/qcom/qcm2290.dtsi | 50 +++++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi > index 7fb5de92bc4c..43fcb4f40a8c 100644 > --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi > @@ -557,6 +557,20 @@ qup_uart4_default: qup-uart4-default-state { > bias-disable; > }; > > + cci0_default: cci0-default-state { > + pins = "gpio22", "gpio23"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + cci1_default: cci1-default-state { > + pins = "gpio29", "gpio30"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-disable; > + }; > + > sdc1_state_on: sdc1-on-state { > clk-pins { > pins = "sdc1_clk"; > @@ -1603,6 +1617,42 @@ adreno_smmu: iommu@59a0000 { > #iommu-cells = <2>; > }; > > + cci: cci@5c1b000 { > + compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci"; > + reg = <0x0 0x5c1b000 0x0 0x1000>; > + > + interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>; > + > + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>; > + clock-names = "camss_top_ahb", "cci"; do you not need an axi clock GCC_CAMSS_AXI_CLK ? > + assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>; > + assigned-clock-rates = <37500000>; > + > + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; > + > + pinctrl-0 = <&cci0_default &cci1_default>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + cci_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <400000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <400000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > mdss: display-subsystem@5e00000 { > compatible = "qcom,qcm2290-mdss"; > reg = <0x0 0x05e00000 0x0 0x1000>; > -- > 2.34.1 > > other than that Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 7fb5de92bc4c..43fcb4f40a8c 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -557,6 +557,20 @@ qup_uart4_default: qup-uart4-default-state { bias-disable; }; + cci0_default: cci0-default-state { + pins = "gpio22", "gpio23"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + + cci1_default: cci1-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; @@ -1603,6 +1617,42 @@ adreno_smmu: iommu@59a0000 { #iommu-cells = <2>; }; + cci: cci@5c1b000 { + compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci"; + reg = <0x0 0x5c1b000 0x0 0x1000>; + + interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>; + + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>; + clock-names = "camss_top_ahb", "cci"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>; + assigned-clock-rates = <37500000>; + + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; + + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + mdss: display-subsystem@5e00000 { compatible = "qcom,qcm2290-mdss"; reg = <0x0 0x05e00000 0x0 0x1000>;
Add Camera Control Interface (CCI), supporting two I2C masters. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> --- v2: Reorder commits; Update dts properties order and style v3: No change for this patch arch/arm64/boot/dts/qcom/qcm2290.dtsi | 50 +++++++++++++++++++++++++++ 1 file changed, 50 insertions(+)