| Message ID | 20250410-hp-x14-v2-1-d36414704a0a@oldschoolsolutions.biz (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: x1e80100-hp-x14: add usb-1-ss1-sbu-mux | expand |
[ +CC: Stephan ] On Thu, Apr 10, 2025 at 12:07:28PM +0200, Jens Glathe via B4 Relay wrote: > From: Jens Glathe <jens.glathe@oldschoolsolutions.biz> > > The usb_1_1 port doesn't have the PS8830 repeater, but apparently some > MUX for DP altmode control. After a suggestion from sgerhold on > '#aarch64-laptops' I added gpio-sbu-mux nodes from the x1e80100-QCP > tree, and this appears to work well. It is still guesswork, but > working guesswork. Did you confirm the three GPIOs experimentally, for example, by making sure that inverting the enable signal polarity breaks USB? > + usb-1-ss1-sbu-mux { > + compatible = "onnn,fsusb42", "gpio-sbu-mux"; > + > + enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; > + select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>; > + > + pinctrl-0 = <&usb_1_ss1_sbu_default>; > + pinctrl-names = "default"; > }; > > &apps_rsc { > @@ -1424,6 +1451,30 @@ reset-n-pins { > }; > }; > > + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { > + mode-pins { > + pins = "gpio177"; > + function = "gpio"; > + bias-disable; > + drive-strength = <2>; > + output-high; > + }; This is more of a question for Stephan who added this to QCP [1], but why is this mode pin here and what does it do? It's not part of the binding for the mux (which indeed only has two control signals according to the datasheet) so it looks like something is not modelled correctly. > + > + oe-n-pins { > + pins = "gpio179"; > + function = "gpio"; > + bias-disable; > + drive-strength = <2>; > + }; > + > + sel-pins { > + pins = "gpio178"; > + function = "gpio"; > + bias-disable; > + drive-strength = <2>; > + }; > + }; Johan [1] https://lore.kernel.org/all/20241212-x1e80100-qcp-dp-v1-2-37cb362a0dfe@linaro.org/
On Fri, Apr 11, 2025 at 01:25:39PM +0200, Johan Hovold wrote: > [ +CC: Stephan ] > > On Thu, Apr 10, 2025 at 12:07:28PM +0200, Jens Glathe via B4 Relay wrote: > > From: Jens Glathe <jens.glathe@oldschoolsolutions.biz> > > > > The usb_1_1 port doesn't have the PS8830 repeater, but apparently some > > MUX for DP altmode control. After a suggestion from sgerhold on > > '#aarch64-laptops' I added gpio-sbu-mux nodes from the x1e80100-QCP > > tree, and this appears to work well. It is still guesswork, but > > working guesswork. > [...] > > @@ -1424,6 +1451,30 @@ reset-n-pins { > > }; > > }; > > > > + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { > > + mode-pins { > > + pins = "gpio177"; > > + function = "gpio"; > > + bias-disable; > > + drive-strength = <2>; > > + output-high; > > + }; > > This is more of a question for Stephan who added this to QCP [1], but > why is this mode pin here and what does it do? > > It's not part of the binding for the mux (which indeed only has two > control signals according to the datasheet) so it looks like something > is not modelled correctly. > I'm afraid you have opened a "can of worms" here. :') On the QCP, there are actually two of these muxes chained for each port. One of them does the orientation switching that we are describing here, the other selects between routing SBU to DP AUX or USB SBTX/SBRX. I'm guessing this is meant for USB4. Given that: - We don't have any support for USB4 on QC platforms at the moment. - We're not modelling the USB4 stuff for the retimer either(?). - We have no clear overview of what/how to model for USB4. - The ports without retimer aren't advertised with USB4 support (I'm guessing the signal quality is not reliable enough without retimer). - The gpio-sbu-mux driver doesn't support shared enable-gpios. ... we just went with the tradeoff of forcing DP AUX mode here by setting a fixed state for the second mux. I'm not sure if the other configuration is even a valid use case for the ports without retimer. A comment about this would have been nice, but I didn't think of that anymore when cleaning up the patches. :-) Thanks, Stephan
On Fri, Apr 11, 2025 at 01:52:38PM +0200, Stephan Gerhold wrote: > On Fri, Apr 11, 2025 at 01:25:39PM +0200, Johan Hovold wrote: > > > + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { > > > + mode-pins { > > > + pins = "gpio177"; > > > + function = "gpio"; > > > + bias-disable; > > > + drive-strength = <2>; > > > + output-high; > > > + }; > > > > This is more of a question for Stephan who added this to QCP [1], but > > why is this mode pin here and what does it do? > > > > It's not part of the binding for the mux (which indeed only has two > > control signals according to the datasheet) so it looks like something > > is not modelled correctly. > > I'm afraid you have opened a "can of worms" here. :') Heh. > On the QCP, there are actually two of these muxes chained for each port. > One of them does the orientation switching that we are describing here, > the other selects between routing SBU to DP AUX or USB SBTX/SBRX. I'm > guessing this is meant for USB4. Given that: > > - We don't have any support for USB4 on QC platforms at the moment. > - We're not modelling the USB4 stuff for the retimer either(?). > - We have no clear overview of what/how to model for USB4. > - The ports without retimer aren't advertised with USB4 support (I'm > guessing the signal quality is not reliable enough without retimer). > - The gpio-sbu-mux driver doesn't support shared enable-gpios. > > ... we just went with the tradeoff of forcing DP AUX mode here by > setting a fixed state for the second mux. I'm not sure if the other > configuration is even a valid use case for the ports without retimer. > > A comment about this would have been nice, but I didn't think of that > anymore when cleaning up the patches. :-) Thanks for the explanation. Makes sense. Johan
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts index 26ea1787e5ecfb727a4f890895b7d7fb7b3f005d..582d4326d5d527d20f99e716349ea0e9c0d35099 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts @@ -153,6 +153,14 @@ pmic_glink_ss1_ss_in: endpoint { remote-endpoint = <&usb_1_ss1_qmpphy_out>; }; }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_sbu: endpoint { + remote-endpoint = <&usb_1_ss1_sbu_mux>; + }; + }; }; }; }; @@ -477,6 +485,25 @@ vreg_pmu_rfa_1p7: ldo9 { }; }; }; + + usb-1-ss1-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss1_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss1_sbu>; + }; + }; + }; }; &apps_rsc { @@ -1424,6 +1451,30 @@ reset-n-pins { }; }; + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { + mode-pins { + pins = "gpio177"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-high; + }; + + oe-n-pins { + pins = "gpio179"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio178"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio191"; function = "gpio";