| Message ID | 20250412202620.738150-2-ivo.ivanov.ivanov1@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | phy: samsung: add Exynos2200 SNPS eUSB2 driver | expand |
On Sat, Apr 12, 2025 at 11:26:11PM GMT, Ivaylo Ivanov wrote: > Document the exynos2200 eUSB2 compatible. Unlike the currently documented > Qualcomm SoCs, the driver doesn't make use of reset lines for reset > control and uses more clocks. > > Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > --- > .../bindings/phy/samsung,snps-eusb2-phy.yaml | 79 +++++++++++++++++++ > 1 file changed, 79 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/samsung,snps-eusb2-phy.yaml Please name it after compatible, so samsung,exynos2200-eusb2-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/samsung,snps-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,snps-eusb2-phy.yaml > new file mode 100644 > index 000000000..09d3fdd4a > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/samsung,snps-eusb2-phy.yaml > @@ -0,0 +1,79 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/samsung,snps-eusb2-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Samsung SNPS eUSB2 phy controller > + > +maintainers: > + - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > + > +description: > + eUSB2 controller supports LS/FS/HS usb connectivity on Exynos2200. > + > +properties: > + compatible: > + enum: > + - samsung,exynos2200-snps-eusb2-phy I did not mention this earlier, but I think we should skip the snps in the compatible. Using vendor name in device name is just confusing, so: samsung,exynos2200-eusb2-phy However the description should include it, e.g. Samsung Exynos2200 eUSB2 phy, based on Synopsys eUSB2 IP block, .... ... > +additionalProperties: false > + > +examples: > + - | > + usb_hsphy: phy@10ab0000 { > + compatible = "samsung,exynos2200-snps-eusb2-phy"; > + reg = <0x10ab0000 0x10000>; > + #phy-cells = <0>; > + > + clocks = <&cmu_hsi0 7>, > + <&cmu_hsi0 5>, > + <&cmu_hsi0 8>; These should be aligned with opening < With above: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/phy/samsung,snps-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,snps-eusb2-phy.yaml new file mode 100644 index 000000000..09d3fdd4a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/samsung,snps-eusb2-phy.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/samsung,snps-eusb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SNPS eUSB2 phy controller + +maintainers: + - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + +description: + eUSB2 controller supports LS/FS/HS usb connectivity on Exynos2200. + +properties: + compatible: + enum: + - samsung,exynos2200-snps-eusb2-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: Reference clock + - description: Bus (APB) clock + - description: Control clock + + clock-names: + items: + - const: ref + - const: bus + - const: ctrl + + resets: + maxItems: 1 + + phys: + maxItems: 1 + description: + Phandle to eUSB2 to USB 2.0 repeater + + vdd-supply: + description: + Phandle to 0.88V regulator supply to PHY digital circuit. + + vdda12-supply: + description: + Phandle to 1.2V regulator supply to PHY refclk pll block. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - vdd-supply + - vdda12-supply + +additionalProperties: false + +examples: + - | + usb_hsphy: phy@10ab0000 { + compatible = "samsung,exynos2200-snps-eusb2-phy"; + reg = <0x10ab0000 0x10000>; + #phy-cells = <0>; + + clocks = <&cmu_hsi0 7>, + <&cmu_hsi0 5>, + <&cmu_hsi0 8>; + clock-names = "ref", "bus", "ctrl"; + + vdd-supply = <&vreg_0p88>; + vdda12-supply = <&vreg_1p2>; + };
Document the exynos2200 eUSB2 compatible. Unlike the currently documented Qualcomm SoCs, the driver doesn't make use of reset lines for reset control and uses more clocks. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> --- .../bindings/phy/samsung,snps-eusb2-phy.yaml | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/samsung,snps-eusb2-phy.yaml