| Message ID | 20250417-topic-sm8x50-iris-v10-v7-3-f020cb1d0e98@linaro.org (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | media: qcom: iris: add support for SM8650 | expand |
On 4/17/2025 8:29 PM, Neil Armstrong wrote: > Introduce an optional controller_rst_tbl use to store reset lines > used to reset part of the controller. > > This is necessary for the vpu3 support, when the xo reset line > must be asserted separately from the other reset line > on power off operation. > > Factor the iris_init_resets() logic to allow requesting > multiple reset tables. > > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> # x1e Dell > Reviewed-by: Dikshita Agarwal <quic_dikshita@quicinc.com> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > drivers/media/platform/qcom/iris/iris_core.h | 2 ++ > .../platform/qcom/iris/iris_platform_common.h | 2 ++ > drivers/media/platform/qcom/iris/iris_probe.c | 39 +++++++++++++++------- > 3 files changed, 31 insertions(+), 12 deletions(-) > > diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h > index 37fb4919fecc62182784b4dca90fcab47dd38a80..aeeac32a1f6d9a9fa7027e8e3db4d95f021c552e 100644 > --- a/drivers/media/platform/qcom/iris/iris_core.h > +++ b/drivers/media/platform/qcom/iris/iris_core.h > @@ -43,6 +43,7 @@ struct icc_info { > * @clock_tbl: table of iris clocks > * @clk_count: count of iris clocks > * @resets: table of iris reset clocks > + * @controller_resets: table of controller reset clocks > * @iris_platform_data: a structure for platform data > * @state: current state of core > * @iface_q_table_daddr: device address for interface queue table memory > @@ -82,6 +83,7 @@ struct iris_core { > struct clk_bulk_data *clock_tbl; > u32 clk_count; > struct reset_control_bulk_data *resets; > + struct reset_control_bulk_data *controller_resets; > const struct iris_platform_data *iris_platform_data; > enum iris_core_state state; > dma_addr_t iface_q_table_daddr; > diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h > index f6b15d2805fb2004699709bb12cd7ce9b052180c..fdd40fd80178c4c66b37e392d07a0a62f492f108 100644 > --- a/drivers/media/platform/qcom/iris/iris_platform_common.h > +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h > @@ -156,6 +156,8 @@ struct iris_platform_data { > unsigned int clk_tbl_size; > const char * const *clk_rst_tbl; > unsigned int clk_rst_tbl_size; > + const char * const *controller_rst_tbl; > + unsigned int controller_rst_tbl_size; > u64 dma_mask; > const char *fwname; > u32 pas_id; > diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c > index aca442dcc153830e6252d1dca87afb38c0b9eb8f..4f8bce6e2002bffee4c93dcaaf6e52bf4e40992e 100644 > --- a/drivers/media/platform/qcom/iris/iris_probe.c > +++ b/drivers/media/platform/qcom/iris/iris_probe.c > @@ -91,25 +91,40 @@ static int iris_init_clocks(struct iris_core *core) > return 0; > } > > -static int iris_init_resets(struct iris_core *core) > +static int iris_init_reset_table(struct iris_core *core, > + struct reset_control_bulk_data **resets, > + const char * const *rst_tbl, u32 rst_tbl_size) > { > - const char * const *rst_tbl; > - u32 rst_tbl_size; > u32 i = 0; > > - rst_tbl = core->iris_platform_data->clk_rst_tbl; > - rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size; > - > - core->resets = devm_kzalloc(core->dev, > - sizeof(*core->resets) * rst_tbl_size, > - GFP_KERNEL); > - if (!core->resets) > + *resets = devm_kzalloc(core->dev, > + sizeof(struct reset_control_bulk_data) * rst_tbl_size, > + GFP_KERNEL); > + if (!*resets) > return -ENOMEM; > > for (i = 0; i < rst_tbl_size; i++) > - core->resets[i].id = rst_tbl[i]; > + (*resets)[i].id = rst_tbl[i]; > + > + return devm_reset_control_bulk_get_exclusive(core->dev, rst_tbl_size, *resets); > +} > + > +static int iris_init_resets(struct iris_core *core) > +{ > + int ret; > + > + ret = iris_init_reset_table(core, &core->resets, > + core->iris_platform_data->clk_rst_tbl, > + core->iris_platform_data->clk_rst_tbl_size); > + if (ret) > + return ret; > + > + if (!core->iris_platform_data->controller_rst_tbl_size) > + return 0; > > - return devm_reset_control_bulk_get_exclusive(core->dev, rst_tbl_size, core->resets); > + return iris_init_reset_table(core, &core->controller_resets, > + core->iris_platform_data->controller_rst_tbl, > + core->iris_platform_data->controller_rst_tbl_size); > } > > static int iris_init_resources(struct iris_core *core) > Reviewed-by: Vikash Garodia <quic_vgarodia@quicinc.com>
diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index 37fb4919fecc62182784b4dca90fcab47dd38a80..aeeac32a1f6d9a9fa7027e8e3db4d95f021c552e 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -43,6 +43,7 @@ struct icc_info { * @clock_tbl: table of iris clocks * @clk_count: count of iris clocks * @resets: table of iris reset clocks + * @controller_resets: table of controller reset clocks * @iris_platform_data: a structure for platform data * @state: current state of core * @iface_q_table_daddr: device address for interface queue table memory @@ -82,6 +83,7 @@ struct iris_core { struct clk_bulk_data *clock_tbl; u32 clk_count; struct reset_control_bulk_data *resets; + struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; enum iris_core_state state; dma_addr_t iface_q_table_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index f6b15d2805fb2004699709bb12cd7ce9b052180c..fdd40fd80178c4c66b37e392d07a0a62f492f108 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -156,6 +156,8 @@ struct iris_platform_data { unsigned int clk_tbl_size; const char * const *clk_rst_tbl; unsigned int clk_rst_tbl_size; + const char * const *controller_rst_tbl; + unsigned int controller_rst_tbl_size; u64 dma_mask; const char *fwname; u32 pas_id; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index aca442dcc153830e6252d1dca87afb38c0b9eb8f..4f8bce6e2002bffee4c93dcaaf6e52bf4e40992e 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -91,25 +91,40 @@ static int iris_init_clocks(struct iris_core *core) return 0; } -static int iris_init_resets(struct iris_core *core) +static int iris_init_reset_table(struct iris_core *core, + struct reset_control_bulk_data **resets, + const char * const *rst_tbl, u32 rst_tbl_size) { - const char * const *rst_tbl; - u32 rst_tbl_size; u32 i = 0; - rst_tbl = core->iris_platform_data->clk_rst_tbl; - rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size; - - core->resets = devm_kzalloc(core->dev, - sizeof(*core->resets) * rst_tbl_size, - GFP_KERNEL); - if (!core->resets) + *resets = devm_kzalloc(core->dev, + sizeof(struct reset_control_bulk_data) * rst_tbl_size, + GFP_KERNEL); + if (!*resets) return -ENOMEM; for (i = 0; i < rst_tbl_size; i++) - core->resets[i].id = rst_tbl[i]; + (*resets)[i].id = rst_tbl[i]; + + return devm_reset_control_bulk_get_exclusive(core->dev, rst_tbl_size, *resets); +} + +static int iris_init_resets(struct iris_core *core) +{ + int ret; + + ret = iris_init_reset_table(core, &core->resets, + core->iris_platform_data->clk_rst_tbl, + core->iris_platform_data->clk_rst_tbl_size); + if (ret) + return ret; + + if (!core->iris_platform_data->controller_rst_tbl_size) + return 0; - return devm_reset_control_bulk_get_exclusive(core->dev, rst_tbl_size, core->resets); + return iris_init_reset_table(core, &core->controller_resets, + core->iris_platform_data->controller_rst_tbl, + core->iris_platform_data->controller_rst_tbl_size); } static int iris_init_resources(struct iris_core *core)