diff mbox series

dt-bindings: arm/cpus: allow up to 3 interconnects entries

Message ID 20250418-topic-sm8x50-upstream-cpu-icc-max3-v1-1-87d9c2713d72@linaro.org (mailing list archive)
State New
Headers show
Series dt-bindings: arm/cpus: allow up to 3 interconnects entries | expand

Commit Message

Neil Armstrong April 18, 2025, 12:56 p.m. UTC 
Allow up to 3 entries as used on the Qualcomm SM8650 CPU nodes.

This fixes the following errors:
cpu@0: interconnects: [[7, 3, 3, 7, 15, 3], [8, 0, 3, 8, 1, 3], [9, 0, 9, 1]] is too long

Fixes: 791a3fcd2345 ("dt-bindings: arm/cpus: Add missing properties")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 Documentation/devicetree/bindings/arm/cpus.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


---
base-commit: bc8aa6cdadcc00862f2b5720e5de2e17f696a081
change-id: 20250418-topic-sm8x50-upstream-cpu-icc-max3-731ecf2a9402

Best regards,
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 3d61313ca00ea4fc50f07f1e353be49ddc2377fa..f04ce5355806e6bd575aa1f7c0a69d0b3b605fbf 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -301,7 +301,7 @@  properties:
 
   interconnects:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
 
   nvmem-cells:
     maxItems: 1