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Fri, 9 Jun 2023 19:56:19 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%6]) with mapi id 15.20.6455.030; Fri, 9 Jun 2023 19:56:19 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Christophe Leroy , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kevin Tian , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Russell King , linuxppc-dev@lists.ozlabs.org, Matthias Brugger , Matthew Rosato , Michael Ellerman , Nicholas Piggin , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Dmitry Osipenko , Marek Szyprowski , Nicolin Chen , Niklas Schnelle , Steven Price , Thierry Reding Subject: [PATCH v3 23/25] iommu: Add ops->domain_alloc_paging() Date: Fri, 9 Jun 2023 16:56:11 -0300 Message-Id: <23-v3-89830a6c7841+43d-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v3-89830a6c7841+43d-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: SJ0PR05CA0111.namprd05.prod.outlook.com (2603:10b6:a03:334::26) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DM4PR12MB5264:EE_ X-MS-Office365-Filtering-Correlation-Id: 4c97eff1-1f2c-4755-8774-08db69239630 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /hfFcSRjURBzQ0ts0Vn2L2sxCEAyVfXgoRyKH//EME/HHox5USw/l+Dh9wHF6utPKnrNXNBWIBFybU9dy1Y7Ytmj4bU59Drj+AbjgeRHzo9wj2khVXMXFZibOky5jnTjfm6dO7r+R/QuzGB6CczDcUThUaQ/rkcNiXcnwTaZWFjoGUBc8JHJ+krZT7ncdr+8y9COmzCzycB0OFJLMuaCtsClFGEJ+V2if+QMu+yHHiwOc0zd1DgjUWzL+Qylk8q9zX8XotzIDZRCu3/O1amJB5tmlpTzWllcblP5B/Cq/X/GmJNN577LnbJWRh39WztvO1Q3z14bX6/n8EVtaqLY24Olgx/fXdJE4ufbVgRdXNU7UbsUCMwk60ZRycMZyBeRNlP+IOnb0ebTBIy3h630rfuQyHKsqqK67hlZBmkWUE18feckuUSZY7fxyJjGGWXmHZy5gaT5xaEW/62XKPzdtr1aBZWa+X/NrWBRjbxHiB49SDmsglVhnrYrVEuQBwU6jw7LAT2Xbwe/V0RtLePBbRrB7srCzFcWv0jS9wCuaxwNL6hvvsRefqbKkflLA2SQEDU85KOhd6D8FexKXMg6ulMR7viRS2VjL8338GqKVuJa888U+yJf5uAnulLvvmBSMkkJAN5SFnfa/EASaiEmWmjUdKLp32GSmud6dNe1xPAGOi088q9tQowu1IrkgiBT4pEfenFWp8RJKYpNRnntU/OhBKqtW+jHRibYQVLNP36XOA678jDSsmj4KbNc0nWEe3ASL3bco+u7TJyDxi3ZDADya44aVRSWGCJL/REUAb+XriHlWJXfQNZyd8nnVyDSt7OXmsfqmOMw8s/9kMIN/6j01DnNeXwjsOP2EZu//994lEU4P9gTqzNEcjou+kYN5K430uWlpumt4/uIr+FkjbzKZFEkEkY+ykHfKPYz4PXZBQj3txCLUzmqWS8E+ADHoQAdQelMrEm2Q3+APTHphFvg5rhtk+teOwAIiyf/fSfeDIPvGqsvGfqJkVxFZBmITOdy2Y/mxxe9TJCGHeZvrH91TOXcLkoqmvkXn60DihcRe8e24f/SRvZzOblXE6vTj6neVl/kiLsbl0ZaAhXa8wweu63SkO/3TrM6lQmyWawdVf3cvmkQl15SCUegRMX5mJ1rT0DY3M+onUkGEyDt1zkRoppxA6aD1IuznBcIsIKEMsaumJChhhoPYeNFpxwtIPmMeT8ruxFlzsoimVXJRylqpOkmA87MmrWSGHNmfHQSZ77XmdnQgm1HRb7x5pS34zwMR1XAKZj/psNP2+4BMXBELV8pNln8swprqrL6obhePOg38D/xkTFG/4X4d+jHAg55PpQRr7Vv31m3ZmkSUBzRKnHrk++gnF2PBaoefAa9xDcpJpaHzLtiba8Me3/ahgR+G/FjFoCXw9vJBRgBLQxXuB/4Zr8N9beDS3I80M7DqGCdZzjje60sKgNIqnFRbmA6ZpBMD+Hr4Tjsdph48HwQyjavNimckRaaluaJGoh8ZvJlDk1FFe8NOJgQej6mSrKC913SFtBqg5BMsdYn8nE+9mzvwi/B3ZPdYSyglBHC8Xp5zxwKWg7eGgg/6l/X X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4c97eff1-1f2c-4755-8774-08db69239630 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2023 19:56:17.0704 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ohIGnzWOipZ4w8Rv8OVzfZrXgSEcaqWbuBwVrdqWsa3cpJ0YNPeIVT40DS4kYJK6 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5264 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This callback requests the driver to create only a __IOMMU_DOMAIN_PAGING domain, so it saves a few lines in a lot of drivers needlessly checking the type. More critically, this allows us to sweep out all the IOMMU_DOMAIN_UNMANAGED and IOMMU_DOMAIN_DMA checks from a lot of the drivers, simplifying what is going on in the code and ultimately removing the now-unused special cases in drivers where they did not support IOMMU_DOMAIN_DMA. domain_alloc_paging() should return a struct iommu_domain that is functionally compatible with ARM_DMA_USE_IOMMU, dma-iommu.c and iommufd. Be forwards looking and pass in a 'struct device *' argument. We can provide this when allocating the default_domain. No drivers will look at this. Tested-by: Steven Price Tested-by: Marek Szyprowski Tested-by: Nicolin Chen Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 13 ++++++++++--- include/linux/iommu.h | 3 +++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 0346c05e108438..2cf523ff9c6f55 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1985,6 +1985,7 @@ void iommu_set_fault_handler(struct iommu_domain *domain, EXPORT_SYMBOL_GPL(iommu_set_fault_handler); static struct iommu_domain *__iommu_domain_alloc(const struct iommu_ops *ops, + struct device *dev, unsigned int type) { struct iommu_domain *domain; @@ -1992,8 +1993,13 @@ static struct iommu_domain *__iommu_domain_alloc(const struct iommu_ops *ops, if (alloc_type == IOMMU_DOMAIN_IDENTITY && ops->identity_domain) return ops->identity_domain; + else if (type & __IOMMU_DOMAIN_PAGING) { + domain = ops->domain_alloc_paging(dev); + } else if (ops->domain_alloc) + domain = ops->domain_alloc(alloc_type); + else + return NULL; - domain = ops->domain_alloc(alloc_type); if (!domain) return NULL; @@ -2024,14 +2030,15 @@ __iommu_group_domain_alloc(struct iommu_group *group, unsigned int type) lockdep_assert_held(&group->mutex); - return __iommu_domain_alloc(dev_iommu_ops(dev), type); + return __iommu_domain_alloc(dev_iommu_ops(dev), dev, type); } struct iommu_domain *iommu_domain_alloc(const struct bus_type *bus) { if (bus == NULL || bus->iommu_ops == NULL) return NULL; - return __iommu_domain_alloc(bus->iommu_ops, IOMMU_DOMAIN_UNMANAGED); + return __iommu_domain_alloc(bus->iommu_ops, NULL, + IOMMU_DOMAIN_UNMANAGED); } EXPORT_SYMBOL_GPL(iommu_domain_alloc); diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 49331573f1d1f5..8e4d178c49c417 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -233,6 +233,8 @@ struct iommu_iotlb_gather { * struct iommu_ops - iommu ops and capabilities * @capable: check capability * @domain_alloc: allocate iommu domain + * @domain_alloc_paging: Allocate an iommu_domain that can be used for + * UNMANAGED, DMA, and DMA_FQ domain types. * @probe_device: Add device to iommu driver handling * @release_device: Remove device from iommu driver handling * @probe_finalize: Do final setup work after the device is added to an IOMMU @@ -264,6 +266,7 @@ struct iommu_ops { /* Domain allocation and freeing by the iommu driver */ struct iommu_domain *(*domain_alloc)(unsigned iommu_domain_type); + struct iommu_domain *(*domain_alloc_paging)(struct device *dev); struct iommu_device *(*probe_device)(struct device *dev); void (*release_device)(struct device *dev);