| Message ID | 249bddc521b15e992d0846edf1813aeb577458b9.1621851644.git.baruch@tkos.co.il (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2,1/3] pwm: driver for qualcomm ipq6018 pwm block | expand |
On Mon, May 24, 2021 at 01:20:43PM +0300, Baruch Siach wrote: > DT binding for the PWM block in Qualcomm IPQ6018 SoC. > > Signed-off-by: Baruch Siach <baruch@tkos.co.il> > --- > v2: Make #pwm-cells const (Rob Herring) > --- > .../devicetree/bindings/pwm/ipq-pwm.yaml | 52 +++++++++++++++++++ > 1 file changed, 52 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > new file mode 100644 > index 000000000000..f85ce808a14e > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > @@ -0,0 +1,52 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm IPQ6018 PWM controller > + > +maintainers: > + - Baruch Siach <baruch@tkos.co.il> > + > +properties: > + "#pwm-cells": > + const: 2 > + > + compatible: > + const: qcom,pwm-ipq6018 qcom,ipq6018-pwm is the normal ordering. > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: core > + > +required: > + - "#pwm-cells" > + - compatible > + - reg > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-ipq6018.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pwm@1941010 { > + #pwm-cells = <2>; > + compatible = "qcom,pwm-ipq6018"; > + reg = <0x0 0x1941010 0x0 0x20>; > + clocks = <&gcc GCC_ADSS_PWM_CLK>; > + clock-names = "core"; > + }; > + }; > -- > 2.30.2
On Mon 24 May 05:20 CDT 2021, Baruch Siach wrote: > DT binding for the PWM block in Qualcomm IPQ6018 SoC. > > Signed-off-by: Baruch Siach <baruch@tkos.co.il> > --- > v2: Make #pwm-cells const (Rob Herring) > --- > .../devicetree/bindings/pwm/ipq-pwm.yaml | 52 +++++++++++++++++++ > 1 file changed, 52 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > new file mode 100644 > index 000000000000..f85ce808a14e > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > @@ -0,0 +1,52 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm IPQ6018 PWM controller > + > +maintainers: > + - Baruch Siach <baruch@tkos.co.il> > + > +properties: > + "#pwm-cells": > + const: 2 > + > + compatible: > + const: qcom,pwm-ipq6018 > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: core > + > +required: > + - "#pwm-cells" > + - compatible > + - reg > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-ipq6018.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pwm@1941010 { > + #pwm-cells = <2>; > + compatible = "qcom,pwm-ipq6018"; > + reg = <0x0 0x1941010 0x0 0x20>; These 32 bytes are in the middle of the TCSR block, which is already partially described by the &tcsr_q6 node, which is described as only compatible = "syscon" - something no longer accepted by the DT maintainers. As such, I think we should adjust the &tcsr_q6 definition to cover the entire TCSR: 0x01937000 of size 0x21000. @Rob, should we represent the entire tcsr as a simple-mfd and then have the pwm and q6 region as children of that? Or can we make the whole thing as a simple-mfd and a syscon and only describe the pwm as a child? Regards, Bjorn > + clocks = <&gcc GCC_ADSS_PWM_CLK>; > + clock-names = "core"; > + }; > + }; > -- > 2.30.2 >
On 2021-06-03 04:35, Bjorn Andersson wrote: > On Mon 24 May 05:20 CDT 2021, Baruch Siach wrote: > >> DT binding for the PWM block in Qualcomm IPQ6018 SoC. >> >> Signed-off-by: Baruch Siach <baruch@tkos.co.il> >> --- >> v2: Make #pwm-cells const (Rob Herring) >> --- >> .../devicetree/bindings/pwm/ipq-pwm.yaml | 52 >> +++++++++++++++++++ >> 1 file changed, 52 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml >> >> diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml >> b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml >> new file mode 100644 >> index 000000000000..f85ce808a14e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml >> @@ -0,0 +1,52 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm IPQ6018 PWM controller >> + >> +maintainers: >> + - Baruch Siach <baruch@tkos.co.il> >> + >> +properties: >> + "#pwm-cells": >> + const: 2 >> + >> + compatible: >> + const: qcom,pwm-ipq6018 >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + const: core >> + >> +required: >> + - "#pwm-cells" >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/clock/qcom,gcc-ipq6018.h> >> + >> + soc { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + pwm@1941010 { >> + #pwm-cells = <2>; >> + compatible = "qcom,pwm-ipq6018"; >> + reg = <0x0 0x1941010 0x0 0x20>; > > These 32 bytes are in the middle of the TCSR block, which is already > partially described by the &tcsr_q6 node, which is described as only > compatible = "syscon" - something no longer accepted by the DT > maintainers. > > As such, I think we should adjust the &tcsr_q6 definition to cover the > entire TCSR: 0x01937000 of size 0x21000. > To my knowledge, we can cover the entire TCSR region, so that we can use it for the other features like qcom,dload-mode as well. > > @Rob, should we represent the entire tcsr as a simple-mfd and then have > the pwm and q6 region as children of that? Or can we make the whole > thing as a simple-mfd and a syscon and only describe the pwm as a > child? > > Regards, > Bjorn > >> + clocks = <&gcc GCC_ADSS_PWM_CLK>; >> + clock-names = "core"; >> + }; >> + }; >> -- >> 2.30.2 >>
diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml new file mode 100644 index 000000000000..f85ce808a14e --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - Baruch Siach <baruch@tkos.co.il> + +properties: + "#pwm-cells": + const: 2 + + compatible: + const: qcom,pwm-ipq6018 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: core + +required: + - "#pwm-cells" + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq6018.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pwm@1941010 { + #pwm-cells = <2>; + compatible = "qcom,pwm-ipq6018"; + reg = <0x0 0x1941010 0x0 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + clock-names = "core"; + }; + };
DT binding for the PWM block in Qualcomm IPQ6018 SoC. Signed-off-by: Baruch Siach <baruch@tkos.co.il> --- v2: Make #pwm-cells const (Rob Herring) --- .../devicetree/bindings/pwm/ipq-pwm.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml